DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-15 and 17-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 12 is objected to because of the following informalities: Applicant claims a method step of “forming a structured dielectric…” in line 14. This is a method step provided in a device claim. This limitation is being interpreted as “a structured dielectric...” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 11-15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chi et al. (US Publication No. 2011/0291249) in view of Dahilig et al. (US Publication No. 2010/0320588).
Regarding claim 1, Chi discloses a method for manufacturing a semiconductor package (Figures 3 and 6), the method comprising:
providing an electrically conductive chip carrier (122) comprising a mounting surface (upper surface of 124) and a protrusion (126) extending out of the mounting surface (Figure 3 and 6A)
arranging at least one semiconductor chip (130) on the mounting surface (Figure 6A), the at least one semiconductor chip including one or more chip electrodes (170)
encapsulating (172) the protrusion (126) and the at least one semiconductor chip (130) in an encapsulation material (Figure 6B), wherein surfaces of the protrusion (126) and the at least one semiconductor chip (130) facing away from the mounting surface (124) remain uncovered by the encapsulation material (172) and are arranged substantially on the same level (Figures 3F and 6)
forming an electrical redistribution layer (182), wherein the electrical redistribution layer (182) provides an electrical connection (182) between the protrusion (126) and the at least one semiconductor chip (130) (Figure 7)
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Chi does not clearly disclose the surfaces of the protrusion and the one or more chip electrodes are arranged substantially on the same level, wherein during the encapsulating the encapsulation material is formed such that a top surface of the encapsulating material and the surfaces of the protrusion and of the one or more chip electrodes of the at least one semiconductor chip facing away from the mounting surface are flush with one another to form a common plane, then forming a structured dielectric layer on the common plane, the dielectric layer separate from the encapsulation layer. However, Dahilig discloses the surfaces of the protrusion (128) and the one or more chip electrodes (132) are arranged substantially on the same level, wherein during the encapsulating the encapsulation material (142) is formed such that a top surface of the encapsulating material (142) and the surfaces of the protrusion (128) and of the one or more chip electrodes (132) of the at least one semiconductor chip (130) facing away from the mounting surface are flush with one another to form a common plane (Figure 3F), then forming a structured dielectric layer (158) on the common plane, the dielectric layer separate from the encapsulation layer (142), then forming an electrical redistribution layer on the common plane (top of 130). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Chi to include the common plane for a dielectric and redistribution layer, as taught by Dahilig, since it can minimize manufacturing steps for subsequent build-up without further etching (paragraph 38).
Regarding claim 2, Chi discloses forming the electrical redistribution layer is based on a thin film technology (paragraphs 24 and 26).
Regarding claim 3, Chi discloses encapsulating (172) the protrusion (126) and the at least one semiconductor chip (130) comprises a molding act (paragraph 40; Figure 6B).
Regarding claim 4, Dahilig discloses during the molding act (142) the surfaces of the protrusion (128) and the at least one semiconductor chip (130) facing away from the mounting surface are covered by a film (146), wherein the film (146) is removed after the molding process of the encapsulation material (Figure 3I) to expose the surfaces of the protrusion and of the one or more chip electrodes of the at least one semiconductor chip facing away from the mounting surface from the encapsulation material (Figure 3G). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Chi in view of Dahilig.
Regarding claim 5, Chi discloses during the molding act (172) the film is configured to compensate for height tolerances of at least one of the protrusion (126), the at least one semiconductor chip (130) and a die attach material (132) arranged between the at least one semiconductor chip (130) and the mounting surface (124).
Regarding claim 11, Chi discloses forming a dielectric layer (184) over the electrical redistribution layer (182); and forming a further electrical redistribution layer (186) over the dielectric layer (184), wherein the further electrical redistribution layer (186) is electrically connected to the electrical redistribution layer (182) (Figure 6E).
Regarding claim 12, Chi discloses a semiconductor package, comprising (Figures 3 and 6):
an electrically conductive chip carrier (122) comprising a mounting surface and a carrier portion (126) extending out of the mounting surface (124) arranged laterally displaced to the mounting surface (Figures 3 and 6A)
at least one semiconductor chip (130) arranged on the mounting surface (124), the at least one semiconductor ship including one or more chip electrodes (Figure 6A)
an encapsulation material (172) encapsulating the carrier portion (126) and the at least one semiconductor chip (130), wherein surfaces of the carrier portion (126) and of the one or more chip electrodes of the at least one semiconductor chip (130) facing away from the mounting surface (124) are uncovered by the encapsulation material (172) and are arranged substantially on the same level (Figures 3 and 6C)
an electrical redistribution layer (182), wherein the electrical redistribution layer (182) provides an electrical connection (170/182) between the carrier portion (126) and the at least one semiconductor chip (130) (Figures 3 and 6D)
Chi does not clearly disclose the surfaces of the protrusion and the one or more chip electrodes are arranged substantially on the same level, wherein during the encapsulating the encapsulation material is formed such that a top surface of the encapsulating material and the surfaces of the protrusion and of the one or more chip electrodes of the at least one semiconductor chip facing away from the mounting surface are flush with one another to form a common plane, then forming a structured dielectric layer on the common plane, the dielectric layer separate from the encapsulation layer. However, Dahilig discloses the surfaces of the protrusion (128) and the one or more chip electrodes (132) are arranged substantially on the same level, wherein during the encapsulating the encapsulation material (142) is formed such that a top surface of the encapsulating material (142) and the surfaces of the protrusion (128) and of the one or more chip electrodes (132) of the at least one semiconductor chip (130) facing away from the mounting surface are flush with one another to form a common plane (Figure 3F), then forming a structured dielectric layer (158) on the common plane, the dielectric layer separate from the encapsulation layer (142), then forming an electrical redistribution layer on the common plane (top of 130). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Chi to include the common plane for a dielectric and redistribution layer, as taught by Dahilig, since it can minimize manufacturing steps for subsequent build-up without further etching (paragraph 38).
Regarding claim 13, Chi discloses the electrical redistribution layer comprises a thin film electrical redistribution layer (paragraphs 24 and 26).
Regarding claim 14, Chi discloses the chip carrier (126) comprises a leadframe (120) (paragraph 37).
Regarding claim 15, Chi discloses the carrier portion (126) forms an electrical through connection (126) extending from a first surface (upper surface of 172) of the encapsulation material (172) to a second surface (lower surface of 172) of the encapsulation material (172) opposite to the first surface (Figure 7; paragraph 58).
Regarding claim 17, Chi discloses the surfaces of the carrier portion (126) and the at least one semiconductor chip (130) facing away from the mounting surface (124) are flush with a surface of the encapsulation material (172) (Figure 7).
Regarding claim 18, Chi discloses the electrically conductive chip carrier (122) is structured at a surface of the electrically conductive chip carrier opposite to the mounting surface (124), thereby forming electric contact elements (196) configured for a connection to a printed circuit board (The external solder connections 196 are inherently configured to attached to a printed circuit board, as shown in the embodiment of Figure 2C).
Claims 1, 4, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Dahilig et al. (US Publication No. 2010/0320588) in view of Chi et al. (US Publication No. 2011/0291249).
Regarding claim 1, Dahilig discloses a method for manufacturing a semiconductor package (Figure 3), the method comprising:
providing an electrically conductive chip carrier (124) comprising a mounting surface (126) and a protrusion (128) extending out of the mounting surface (126)
arranging at least one semiconductor chip (130) on the mounting surface (126), the at least one semiconductor chip including one or more chip electrodes (132)
encapsulating (142) the protrusion (128) and the at least one semiconductor chip (130) in an encapsulation material (142), wherein surfaces of the protrusion (128) and the at least one semiconductor chip (130) facing away from the mounting surface (126) remain uncovered by the encapsulation material (142) and are arranged substantially on the same level, and wherein during the encapsulating the encapsulation material is formed such that a top surface of the encapsulating material (142) and the surfaces of the protrusion (128) and of the one or more chip electrodes (132) of the at least one semiconductor chip (130) facing away from the mounting surface are flush with one another to form a common plane (Figure 3F)
forming a structured dielectric layer (158) on the common plane, the dielectric layer separate from the encapsulation material (142)
forming an electrical redistribution layer (154) on the common plane (top of 130)
Dahilig does not disclose the electrical redistribution layer provides an electrical connection between the protrusion and the at least one semiconductor chip. However, Chi discloses an electrical redistribution layer (180) which provides an electrical connection (182) between the protrusion (126) and the at least one semiconductor chip (130) (Figure 6D). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Dahilig to include a connection between the protrusion and chip, as taught by Chi, since it can provide heat spreading and additional electrical interconnect and package integration (paragraph 58).
Regarding claim 4, Dahilig discloses during the molding act (142) the surfaces of the protrusion (128) and the at least one semiconductor chip (130) facing away from the mounting surface are covered by a film (146), wherein the film (146) is removed after the molding process of the encapsulation material (Figure 3I) to expose the surfaces of the protrusion and of the one or more chip electrodes of the at least one semiconductor chip facing away from the mounting surface from the encapsulation material (Figure 3G).
Regarding claim 12, Dahilig discloses a semiconductor package, comprising (Figures 3):
an electrically conductive chip carrier (124) comprising a mounting surface (126) and a carrier portion (128) extending out of the mounting surface arranged laterally displaced to the mounting surface (126)
at least one semiconductor chip (130) arranged on the mounting surface, the at least one semiconductor chip (130) including one or more chip electrodes (132)
an encapsulation material encapsulating the carrier portion (128) and the at least one semiconductor chip (130), wherein surfaces of the carrier portion (128) and the at least one semiconductor chip (130) facing away from the mounting surface (126) are uncovered by the encapsulation material (142) and are arranged substantially on the same level, and wherein a top surface of the encapsulating material and the surfaces of the carrier portion (128) and of the one or more chip electrodes (132) of the at least one semiconductor chip (130) facing away from the mounting surface are flush with one another to form a common plane (Figure 3F)
a structured dielectric layer (158) on the common plane, the dielectric layer separate from the encapsulation material (142)
an electrical redistribution layer (154) on the common plane (top of 130)
Dahilig does not disclose the electrical redistribution layer provides an electrical connection between the protrusion and the at least one semiconductor chip. However, Chi discloses an electrical redistribution layer (180) which provides an electrical connection (182) between the protrusion (126) and the at least one semiconductor chip (130) (Figure 6D). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Dahilig to include a connection between the protrusion and chip, as taught by Chi, since it can provide heat spreading and additional electrical interconnect and package integration (paragraph 58).
Claims 6-10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chi et al. (US Publication No. 2011/0291249) in view of Dahilig et al. (US Publication No. 2010/0320588), and further in view of Ye (US Publication No. 2015/0162271).
Regarding claim 6, Chi/Dahilig discloses the limitations as discussed in the rejection of claim 1 above. Chi/Dahilig is silent regarding how the chip carrier is formed, by providing a metal sheet; and removing material from a first surface of the metal sheet, thereby forming the protrusion. However, Ye discloses providing a metal sheet and etching to form protrusions of a leadframe (210) (paragraph 64). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have combined the leadframe formation method of Ye with the package formation of Chi, since forming these protrusions can improve reliability because the bonding wires can be reduced in the package assembly, resulting in increased package density (paragraph 34).
Regarding claim 7, Ye discloses removing the material from the first surface comprises etching the first surface (paragraph 64).
Regarding claim 8, Ye discloses structuring a second surface of the metal sheet opposite to the first surface, thereby forming electric contact elements configured for a connection to a printed circuit board (Paragraph 67 shows “leads in the leadframe 210 are exposed from the encapsulant 260, for electrical connection with external circuits, such as a PCB”).
Regarding claim 9, Chi discloses at least one of the electric contact elements (196) is electrically connected to the at least one semiconductor chip (130) via the protrusion and the electrical redistribution layer (182) (paragraph 46).
Regarding claim 10, Ye discloses arranging an electrically insulating material (218) between the electrical contact elements (211/212).
Regarding claim 20, Chi discloses the limitations as discussed in the rejection of claim 12 above. Chi does not specifically disclose the chip carrier comprises a half etched leadframe. However, Ye discloses providing a metal sheet and etching to form protrusions of a leadframe (210) (paragraph 64). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have combined the etched leadframe formation method of Ye with the package formation of Chi, since forming these protrusions can improve reliability because the bonding wires can be reduced in the package assembly, resulting in increased package density (paragraph 34).
Claims 19 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chi et al. (US Publication No. 2011/0291249) in view of Dahilig et al. (US Publication No. 2010/0320588), and further in view of Ahmad (US Patent No. 5,759,875).
Regarding claim 19, Chi/Dahilig discloses the limitations as discussed in the rejection of claim 18 above. Chi/Dahilig does not specifically disclose the encapsulation material is arranged between the carrier portion and the at least one semiconductor chip, the encapsulation material comprises fillers having a filler cut, and a distance between the carrier portion and the at least one semiconductor chip is at least two times the filler cut. However, Ahmad discloses an encapsulation material with fillers and a gap between the leadframe and die, and a desire to minimize the ratio of gap:diameter to .75, which means the diameter is at least 1.3 times the filler cut diameter. Therefore, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the filler cut to be twice that of the distance between the carrier and chip to optimize the viscosity of the encapsulant against the reduction in stress from filler particles (col. 4, lines 53-60, col. 6, lines 35-67), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 21, Chi/Dahilig discloses the limitations as discussed in the rejection of claim 1 above. Chi/Dahilig does not specifically disclose encapsulating the protrusion and the at least one semiconductor chip in the encapsulation material includes filling a gap between the at least one semiconductor chip and the protrusion with the encapsulation material, wherein the encapsulation material includes filler particles having a filler size, and wherein a distance of the gap between the semiconductor chip and the protrusion is at least 2 times the filler size. However, However, Ahmad discloses an encapsulation material with fillers and a gap between the leadframe and die, and a desire to minimize the ratio of gap:diameter to .75, which means the diameter is at least 1.3 times the filler cut diameter. Therefore, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the filler cut to be twice that of the distance between the carrier and chip to optimize the viscosity of the encapsulant against the reduction in stress from filler particles (col. 4, lines 53-60, col. 6, lines 35-67), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 22, Ahmad discloses the filler size is in a range of 15um to 100um (col. 6, lines 35-42). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Chi in view of Dahilig.
Regarding claim 23, Ahmad discloses the filler size is a diameter of the filler particles (col. 6, lines 35-42). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Chi in view of Dahilig.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/N.R.P/ 8/12/2025Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897