Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims #1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., (U.S. Pub. No, 2023/0050514), hereinafter referred to as "Chen" and in view of Arnold et al., (U.S. Pub. No. 2009/0072401), hereinafter referred to as "Arnold".
Chen shows, with respect to claim #1, a trench fabrication method, comprising steps of. providing a semiconductor substrate (fig. #1, item 60) (paragraph 0010); forming a first dielectric layer (fig. #3, item 210) on the semiconductor substrate (paragraph 0021); forming a first photoresist layer (fig. #4, item 250) (paragraph 0025) and patterning the first photoresist layer on the first dielectric layer (paragraph 0026); etching the first dielectric layer using the patterned first photoresist layer as a mask to form a first trench penetrating the first dielectric layer (paragraph 0031), wherein the first trench comprises a first width (fig. #5, item W1) (paragraph 0025); removing the first photoresist layer to expose the first dielectric layer (fig. #5, item 210) (paragraph 0026); forming a sacrificial layer (fig. #6, item 260A) on the first dielectric layer, wherein the sacrificial layer fills in the first trench (fig. #5, item 242) (paragraph 0030); removing a portion of the sacrificial layer to expose the first dielectric layer (fig. #7, item 210) outside the first trench and a top surface of the sacrificial layer in the first trench (paragraph 0031); forming a second dielectric layer (fig. #6, item 260b) on the first dielectric layer (fig. #11, item 206) and the top surface of the sacrificial layer in the first trench (paragraph 0030); forming a second photoresist layer (fig. #6, item 260c) and patterning the second photoresist layer on the second dielectric layer (paragraph 0031); etching the second dielectric layer using the patterned second photoresist layer as a mask to form a second trench (fig. #8, item 208) penetrating the second dielectric layer (paragraph 0031), wherein the second trench align with the sacrificial layer in first trench, wherein the second trench comprises a second width (fig. #8, item W3), and wherein the top surface of the sacrificial layer is exposed from the second trench; and removing the second photoresist layer and the sacrificial layer to form a trench for exposing the semiconductor substrate (paragraph 0032).
Chen substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chen fails to explicitly show, with respect to claim #1, a method comprising wherein the sacrificial layer is on the top surface of the etched first dielectric layer, and fills in the first trench; removing a portion of the sacrificial layer through an etch-back process to expose the top surface of the etched first dielectric layer and to obtain an etched a sacrificial layer filling in the first trench; after the etch-back process, forming a second dielectric layer, wherein the second dielectric laver covers the etched first dielectric layer and the top surface of the etched sacrificial layer in the first trench.
Arnold teaches, with respect to claim #1, a method comprising wherein the sacrificial layer (fig. #2b, item 2710) (paragraph 0103) is on the top surface of the etched first dielectric layer (fig. #2b, item 1230 also shown in fig. #1e, item 2600) (paragraph 0009, 0018-0019), and fills in the first trench (fig. #2a, item 2800); removing a portion of the sacrificial layer through an etch-back process to expose the top surface of the etched first dielectric layer and to obtain an etched a sacrificial layer filling in the first trench (fig. #1f, item 2710) (paragraph 0019); after the etch-back process, forming a second dielectric layer (fig. #2b, item 2900), wherein the second dielectric laver covers the etched first dielectric layer and the top surface of the etched sacrificial layer in the first trench (fig. #2e, item 2960) (paragraph 0103, 0106, 0108).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #1, to modified the invention of Chen as modified by the invention of Arnold, which teaches a method a method comprising wherein the sacrificial layer is on the top surface of the etched first dielectric layer, and fills in the first trench; removing a portion of the sacrificial layer through an etch-back process to expose the top surface of the etched first dielectric layer and to obtain an etched a sacrificial layer filling in the first trench; after the etch-back process, forming a second dielectric layer, wherein the second dielectric laver covers the etched first dielectric layer and the top surface of the etched sacrificial layer in the first trench, to incorporate a structural protective layer insuring proper etching process without damaging the underline areas, as taught by Arnold.
Chen shows, with respect to claim #2, a method wherein the second width (fig. #8, item W3) of the second trench is greater than the first width (fig. #8, item W4) of the first trench (paragraph 0032).
Chen shows, with respect to claim #3, a method wherein the first trench (fig. #8, item 204) and the second trench (fig. #8, item 208) are each axisymmetric, and wherein axes of the first and second trenches are colinear and perpendicular to a top surface of the substrate (paragraph 0032).
Chen shows, with respect to claim #4, a method wherein, between the step of removing the second photoresist layer and the step of removing the sacrificial layer, the step of forming the sacrificial layer and dielectric layer is recurringly performed M times, where M denotes a positive integer greater than or equal to 1 (paragraph 0025, 0026, 0030-0032).
Chen shows, with respect to claim #5, a method wherein the first dielectric layer (fig. #6, item 210) and the second dielectric layer (fig. #6, item 260c) are made of the same material (paragraph 0021, 0030).
Chen shows, with respect to claim #6, a method wherein an aspect ratio of the first trench ranges from 1:1 to 100:1, and an aspect ratio of the second trench ranges from 1:1 to 100:1 (paragraph 0031).
Chen shows, with respect to claim #7, a method wherein the first trench is a deep-hole trench or a deep-groove trench, and wherein the second trench is a deep-hole trench or a deep- groove trench (paragraph 0031).
Chen shows, with respect to claim #8, a method wherein a cross sectional shape of the first trench comprises one of rectangular, inverted-trapezoid, V-shaped and U-shaped, and wherein a cross sectional shape of the second trench comprises one of rectangular, inverted-trapezoid, V-shaped and U-shaped (fig. #8, item 242, 204) (paragraph 0030 0032).
Chen shows, with respect to claim #9, a method wherein the first dielectric layer is one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer, and wherein the second dielectric layer is one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer (paragraph 0013, 0019).
//
Claim #10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., (U.S. Pub. No, 2023/0050514), hereinafter referred to as "Chen" as modified by Arnold et al., (U.S. Pub. No. 2009/0072401), hereinafter referred to as "Arnold" as shown in the rejection of claim #1 above and in further view of Naik et al., (U.S. Pub. No. 2008/0020570), hereinafter referred to as "Naik".
Chen as modified by Arnold, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chen as modified by Arnold, fails to show, with respect to claim #10, a method wherein the sacrificial layer is a BARC layer.
Naik teaches, with respect to claim #10, a method wherein the sacrificial layer is a BARC layer (paragraph 0029).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #10, to modified the invention of Chen as modified by Arnold, with the modification of the invention of Naik, which teaches, a method wherein the sacrificial layer is a BARC layer, to incorporate a structural condition that could be used to control reflections from the underlying dielectric film stack during lithography processes, as taught by Naik.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
05/21/2025 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights