DETAILED ACTION
Response to Amendment
This action is responsive the amendment filed on 12/31/2025. Claims 1-22 are pending and have been examined. Claims 1-22 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9, 16-19 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by NPL reference “Dynamic Cluster Assignment Mechanism” hereby referred to as Canal (cited on IDS filed on 9/26/2022).
In regards to claim 1, Canal discloses An apparatus (See page 2, section 2: wherein processor is disclosed) comprising: a first out-of-order (OOO) execution circuit (See page 2, section 2 and page 4, table 2: wherein cluster 2 is a first OOO execution circuit. Wherein table 2 parameters indicate that each cluster includes out-of-order issuing. Thus, if the execution circuits receive instructions out-of-order they execute instructions for OOO execution) a second out-of-order (OOO) execution circuit that is one or more of narrower and shallower as compared to the first execution circuit (See page 2, section 2 and page 4, table 2: wherein cluster 1 is a second execution circuit that is narrower (restricted) and shallower compared to cluster 2 because cluster 1 only includes simple integer functional units while cluster 2 includes simple and complex integer functional units as well as FP functional units. Wherein table 2 parameters indicate that each cluster includes out-of-order issue. Thus, if the execution circuits receive instructions out-of-order they execute instructions for OOO execution) and circuitry coupled to a first OOO execution circuit and the second OOO execution circuit (See page 2, section 2 and Fig. 1 which discloses steering logic hardware coupled to each cluster) detect an instruction to be executed (see page 2, section 2: wherein steering logic determines which cluster a decoded instruction is to be executed) access tag information which corresponds to a branch sequence which comprises the instruction (see pages 7-8, sections 3.6-3.7: wherein a Slice ID value (tag information) as shown in Fig. 10 which corresponds to a branch sequence (instructions in backward slice of branch) is accessed from a slice table) perform an evaluation, based on the tag information, to determine whether a branch instruction of the branch sequence has been classified as hard to predict (see pages 7-8, sections 3.6-3.7: wherein Slice ID is used to access a cluster table (See Fig. 10) which can be accessed to evaluate and determine if a branch instruction of the branch sequence (instructions in backward slice of branch) has been classified as a branch that is wrongly-predicted often (e.g. a hard to predict branch) when priority slice steering is used by steering logic. Wherein when priority slice steering is used for critical branches that have been classified as hard to predict the cluster table has a flag that indicates the slice as critical and a field that counts a number of branch mispredictions for the slice) perform a selection, based on the evaluation, between the first OOO execution circuit and the second OOO execution circuit; and based on the selection, steer the instruction to one of the first OOO execution circuit or the second OOO execution circuit. (see pages 5 and 7-8, sections 3.4 and 3.6-3.7: wherein priority slice steering is used to select and steer instructions of branch sequences corresponding to critical slices (hard to predict branch sequences) to one of cluster 1 or cluster 2 based on the cluster that the slice is assigned to according to cluster table evaluation (See Fig. 10))
Claim 16 is similarly rejected on the same basis as claim 1 above. (Note: Claim 16 is slightly different in scope as it states “…a front-end unit to decode one or more instructions; an execution engine unit communicatively coupled to the front-end unit to execute one or more decoded instructions…the execution engine unit including a first OOO execution circuit and a second OOO execution circuit that is smaller as compared to the first OOO execution circuit”. However, Canal discloses such limitations “…a front-end unit to decode one or more instructions (page 2, section 2: wherein instructions are fetched and decoded by a centralized hardware) an execution engine unit communicatively coupled to the front-end unit to execute one or more decoded instructions (page 2, section 2: wherein combination of cluster 1 and 2 of Fig. 2 are an execution engine unit communicatively coupled to centralized fetch and decode hardware) the execution engine unit including a first OOO execution circuit and a second OOO execution circuit that is smaller as compared to the first OOO execution circuit (page 2, section 2 and page 4, table 4: wherein cluster 1 is smaller than cluster 2 because cluster 1 has less execution/functional units than cluster 2)”)
In regards to claim 2, Canal discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the instruction to be executed is the branch instruction. (See pages 3, 5 and 7-8, sections 3.1 and 3.6-3.7: wherein the instruction to be executed is the branch instruction)
Claim 17 is similarly rejected on the same basis as claim 2 above.
In regards to claim 3, Canal discloses The apparatus of claim 2 (see rejection of claim 2 above) wherein the circuitry is further to generate the tag information (see page 7, section 3.6 and Fig. 10: wherein steering logic generates Slice ID (tag information)) comprising the circuitry to: identify a frequently mis-predicted branch (See pages 2 and 7-8, sections 2 and 3.7: wherein steering logic identifies a branch in a branch slice which mispredicts very often (also see pages 3 and 5, sections 3.1 and 3.4 for more details on branch slice steering)) form a back-slice chain of instructions that lead up to the frequently mis-predicted branch (See pages 3 and 7-8, sections 3.1 and 3.7: wherein a back-slice chain of instructions that lead up to a critical branch (e.g., a branch mis-predicted often) is disclosed) and identify one or more instructions in the back-slice chain as part of the characteristic branch sequence to be steered to the second OOO execution circuit. (see pages 5 and 7-8, sections 3.4 and 3.7: wherein instructions in back-slice chain of branch slice are steered to the integer cluster)
Claim 18 is similarly rejected on the same basis as claim 3 above.
In regards to claim 4, Canal discloses The apparatus of claim 2 (see rejection of claim 2 above) wherein the circuitry is further to: identify a correct branch after a mis-predicted branch (See pages 2 and 7-8, sections 2 and 3.7: wherein steering logic identifies a correct branch for a branch slice after a mispredicted branch occurs for the branch slice by not updating a count of the number of mispredictions for the branch slice on an occurrence at which the branch does not mispredict (also see pages 3 and 5, sections 3.1 and 3.4 for more details on branch slice steering)) and identify two or more instructions in the correct branch as part of the characteristic branch sequence to be steered to the second OOO execution circuit. (see pages 5 and 7-8, sections 3.4 and 3.7: wherein instructions in back-slice chain of branch slice are steered to the integer cluster)
Claim 19 is similarly rejected on the same basis as claim 4 above.
In regards to claim 9, Canal discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the second OOO execution circuit has a shorter pipeline of execution as compared to the first OOO execution circuit. (see page 2, section 2 and page 4, table 2: wherein cluster 1 has a shorter pipeline of execution as compared to cluster 2 as cluster 1 has less execution units in its pipeline than cluster 2)
Claim 22 is similarly rejected on the same basis as claim 9 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Canal, and further in view of Sheaffer, PGPUB No. 2003/0005261.
In regards to claim 5, Canal discloses The apparatus of claim 1 (see rejection of claim 1 above).
Canal does not disclose wherein the first OOO execution circuit comprises eight or more execution inputs and wherein the second OOO execution circuit comprises less than eight execution inputs.
Sheaffer discloses wherein the first execution circuit comprises eight or more execution inputs and wherein the second execution circuit comprises less than eight execution inputs. ([0027-0028]: wherein an accelerator execution circuit comprises eight execution inputs and regular execution unit comprises four execution inputs)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first and second OOO execution circuits of Canal to respectively comprise eight and four inputs as the first and second execution circuits of Sheaffer. It would have been obvious to one of ordinary skill in the art because it be the simple substitution of one known element (using eight and four execution inputs respectively on a first and second execution circuit as taught in Sheaffer) for another (using generic amount of execution inputs on first and second OOO execution circuits as taught in Canal) to obtain predictable results (a first execution circuit comprising eight execution inputs and a second execution circuit comprising four inputs) (MPEP 2143, Example B). Furthermore, it would have been obvious because the modification can be viewed as a mere duplication of parts (increasing a number of execution inputs) or a change in size/proportion (increase or decrease in a relative number or proportion of execution inputs per execution unit) which the courts have deemed obvious (See MPEP 2144.04(IV(A)) and (VI(B))).
In regards to claim 6, the combination of Canal and Sheaffer discloses The apparatus of claim 5 (see rejection of claim 5 above) wherein the second execution circuit comprises four or less execution inputs. (Sheaffer [0027-0028]: wherein regular execution unit comprises four execution inputs)
Claim 20 is similarly rejected on the same basis as claim 6 above.
Claim(s) 7-8, 10-13, 15 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference “Dynamic Cluster Assignment Mechanism” hereby referred to as Canal (cited on IDS filed on 9/26/2022), and further in view of Sutanto, PGPUB No. 2015/0007188.
In regards to claim 7, Canal discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the first OOO execution circuit comprises reservation station entries per execution input and wherein the second OOO execution circuit comprises reservation station entries per execution input. (See page 2, section 2 and page 4, table 2: wherein cluster 1 and cluster 2 each include issue queue entries per execution unit inputs)
Canal does not disclose wherein the first OOO execution circuit comprises one hundred or more reservation station entries per execution input and wherein the second OOO execution circuit comprises less than one hundred reservation station entries per execution input.
Sutanto discloses wherein an OOO execution circuit comprises one hundred or more reservation station entries per execution input ([0063-0064]: wherein a reservation station comprises 150 or more entries per port) (See Figs. 8-10)) wherein an OOO execution circuit comprises less than one hundred reservation station entries per execution input. (See Figs. 8-10: wherein a reservation station has 18 entries (elements 1001-1019) per dispatch port (see [0080]))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the respective issue queues of Canal to respectively include one hundred or more entries per execution input and less than one hundred entries per execution input as the reservation stations of Sutanto. It would have been obvious to one of ordinary skill in the art because including a number of reservation station entries per execution input utilizes dynamic port binding which improves dispatching performance (Sutanto [0063 and 0090]). Furthermore, it would have been obvious because the modification can be viewed as a change in size/proportion (increase in relative number or proportion of reservation station entries per execution inputs) which the courts have deemed obvious (See MPEP 2144.04(IV(A))).
In regards to claim 8, the combination of Canal and Sutanto discloses The apparatus of claim 7 (see rejection of claim 7 above) wherein the second OOO execution circuit comprises thirty-two or less reservation station entries per execution input. (Sutanto: See Figs. 8-10: wherein an execution circuit has 18 entries (elements 1001-1019) per dispatch port (see [0080]))
Claim 21 is similarly rejected on the same basis as claim 8 above.
In regards to claim 10, Canal discloses a computing device (See page 2, section 2: wherein processor is disclosed) cause the computing device to: detect an instruction to be executed (see page 2, section 2: wherein steering logic determines which cluster a decoded instruction is to be executed) access tag information which corresponds to a branch sequence which comprises the instruction (see pages 7-8, sections 3.6-3.7: wherein a Slice ID value (tag information) as shown in Fig. 10 which corresponds to a branch sequence (instructions in backward slice of branch) is accessed from a slice table) perform an evaluation, based on the tag information, to determine whether a branch instruction of the branch sequence has been classified as hard to predict (see pages 7-8, sections 3.6-3.7: wherein Slice ID is used to access a cluster table (See Fig. 10) which can be accessed to evaluate and determine if a branch instruction of the branch sequence (instructions in backward slice of branch) has been classified as a branch that is wrongly-predicted often (e.g. a hard to predict branch) when priority slice steering is used by steering logic. Wherein when priority slice steering is used for critical branches that have been classified as hard to predict the cluster table has a flag that indicates the slice as critical and a field that counts a number of branch mispredictions for the slice) perform a selection, based on the evaluation, between a first OOO execution circuit and a second OOO execution circuit; and based on the selection, steer the instruction to one of the first OOO execution circuit or the second OOO execution circuit. (see pages 5 and 7-8, sections 3.4 and 3.6-3.7: wherein priority slice steering is used to select and steer instructions of branch sequences corresponding to critical slices (hard to predict branch sequences) to one of cluster 1 or cluster 2 based on the cluster that the slice is assigned to according to cluster table evaluation (See Fig. 10). (Note: table 2 parameters on page 4 indicate that each cluster includes out-of-order issue. Thus, if the execution circuits receive instructions out-of-order they execute instructions for OOO execution)) wherein a second out-of-order OOO execution circuit that is one or more of narrower and shallower as compared to the first OOO execution circuit (See page 2, section 2 and page 4, table 2: wherein cluster 1 is a second execution circuit that is narrower (restricted) and shallower compared to cluster 2 because cluster 1 only includes simple integer functional units while cluster 2 includes simple and complex integer functional units as well as FP functional units. Wherein table 2 parameters indicate that each cluster includes out-of-order issue. Thus, if the execution circuits receive instructions out-of-order they execute instructions for OOO execution)
Canal does not disclose At least one non-transitory machine readable medium comprising a plurality of instructions that, in response to being executed on a computing device.
Sutanto discloses At least one non-transitory machine readable medium comprising a plurality of instructions that, in response to being executed on a computing device. ([0057-0059])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the computing device of Canal to execute instructions stored on a non-transitory readable medium as the device of Sutanto. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (a computing device executing instructions stored on a non-transitory medium as taught in Sutanto) for another (a computing device which executes instructions stored in generic memory as taught in Canal) to obtain predictable results (a computing device operating based on executing instructions stored in a non-transitory computer readable medium) (MPEP 2143, Example B).
In regards to claim 11, the combination of Canal and Sutanto discloses The at least one non-transitory one machine readable medium of claim 10 (see rejection of claim 10 above) wherein the instruction to be executed is the branch instruction. (Canal: See pages 3, 5 and 7-8, sections 3.1 and 3.6-3.7: wherein the instruction to be executed is the branch instruction)
In regards to claim 12, the combination of Canal and Sutanto discloses The at least one non-transitory machine readable medium of claim 11 (see rejection of claim 11 above) comprising a plurality of further instructions that, in response to being executed on the computing device (Sutanto [0057-0059]) cause the computing device to generate the tag information (Canal: see page 7, section 3.6 and Fig. 10: wherein steering logic generates Slice ID (tag information)) comprising the computing device to: identify a frequently mis-predicted branch (Canal: See pages 2 and 7-8, sections 2 and 3.7: wherein steering logic identifies a branch in a branch slice which mispredicts very often (also see pages 3 and 5, sections 3.1 and 3.4 for more details on branch slice steering)) form a back-slice chain of instructions that lead up to the frequently mis-predicted branch (Canal: See pages 3 and 7-8, sections 3.1 and 3.7: wherein a back-slice chain of instructions that lead up to a critical branch (e.g., a branch mis-predicted often) is disclosed) and identify one or more instructions in the back-slice chain as part of the characteristic branch sequence to be steered to the second OOO execution circuit. (Canal: see pages 5 and 7-8, sections 3.4 and 3.7: wherein instructions in back-slice chain of branch slice are steered to the integer cluster)
In regards to claim 13, the combination of Canal and Sutanto discloses The at least one non-transitory machine readable medium of claim 11 (see rejection of claim 11 above) in response to being executed on the computing device (Sutanto [0057-0059]) cause the computing device to: identify a correct branch after a mis-predicted branch (Canal: See pages 2 and 7-8, sections 2 and 3.7: wherein steering logic identifies a correct branch for a branch slice after a mispredicted branch occurs for the branch slice by not updating a count of a number of mispredictions for the branch slice on an occurrence at which the branch does not mispredict (also see pages 3 and 5, sections 3.1 and 3.4 for more details on branch slice steering)) and identify two or more instructions in the correct branch as part of the characteristic branch sequence to be steered to the second OOO execution circuit. (Canal: see pages 5 and 7-8, sections 3.4 and 3.7: wherein instructions in back-slice chain of branch slice are steered to the integer cluster)
In regards to claim 15, the combination of Canal and Sutanto discloses The at least one non-transitory machine readable medium of claim 10 (see rejection of claim 10 above) wherein the second OOO execution circuit has a shorter pipeline of execution as compared to the first OOO execution circuit. (Canal: see page 2, section 2 and page 4, table 2: wherein cluster 1 has a shorter pipeline of execution as compared to cluster 2 as cluster 1 has less execution units in its pipeline than cluster 2)
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference Canal, Sutanto and further in view of Sheaffer.
In regards to claim 14, the combination of Canal and Sutanto thus far discloses The at least one non-transitory machine readable medium of claim 10 (see rejection of claim 10 above).
The combination of Canal and Sutanto thus far does not disclose wherein the first OOO execution circuit comprises eight or more execution ports and wherein the second OOO execution circuit comprises less than eight execution ports and wherein the second OOO execution circuit comprises thirty-two or less reservation station entries per port.
Sutanto discloses wherein an OOO execution circuit comprises thirty-two or less reservation station entries per port. (See Figs. 8-10: wherein a reservation station has 18 entries (elements 1001-1019) per dispatch port (see [0063-0064 and 0080]))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the issue queue of the second execution circuit of Canal to include thirty-two or less entries per execution input as the reservation station of Sutanto. It would have been obvious to one of ordinary skill in the art because including a number of reservation station entries per execution input utilizes dynamic port binding which improves dispatching performance (Sutanto [0063 and 0090]). Furthermore, it would have been obvious because the modification can be viewed as a change in size/proportion (increase or decrease a relative number or proportion of reservation station entries per execution inputs) which the courts have deemed obvious (See MPEP 2144.04(IV(A))).
The combination of Canal and Sutanto does not disclose wherein the first execution circuit comprises eight or more execution ports and wherein the second execution circuit comprises less than eight execution ports.
Sheaffer discloses wherein the first execution circuit comprises eight or more execution ports and wherein the second execution circuit comprises less than eight execution ports. ([0027-0028]: wherein an accelerator execution circuit comprises eight execution inputs and regular execution unit comprises four execution inputs)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first and second execution circuits of Canal and Sutanto to respectively comprise eight and four ports as the first and second execution circuits of Sheaffer. It would have been obvious to one of ordinary skill in the art because it be the simple substitution of one known element (using eight and four execution ports respectively on a first and second execution circuit as taught in Sheaffer) for another (using generic amount of execution ports on a first and second execution circuit as taught in Canal and Sutanto) to obtain predictable results (a first execution circuit comprising eight execution ports and a second execution circuit comprising four ports) (MPEP 2143, Example B). Furthermore, it would have been obvious because the modification can be viewed as a mere duplication of parts (increasing a number of execution ports) or a change in size/proportion (increase or decrease a relative number or proportion of execution ports per execution unit) which the courts have deemed obvious (See MPEP 2144.04(IV(A)) and (VI(B))).
Response to Arguments
Applicant’s arguments, see page 7 of the remarks, filed on 12/31/2025, with respect to previous claim objections and 112(b) rejections have been fully considered and are persuasive. Thus, the previous objections and rejections have been withdrawn.
Applicant's arguments filed on 12/31/2025 have been fully considered but they are not persuasive. The arguments are not persuasive because the NPL reference Canal discloses the argued limitations in the amended independent claims. Therefore, the previous 35 USC 102 and/or 103 rejections in view of Canal and Canal and Sutanto for claims 1, 10 and 16 have been maintained.
Claims 2-9, 11-15 and 17-22 are argued at least based on their respective dependencies and therefore remain rejected based at least on their respective dependencies.
Applicant argues on pages 8-9, of the remarks filed on 12/31/2025, in the substance that:
“However, Caulfield is completely silent as to whether or how (for example) processing pipeline 2 might comprise both the out-of-order execute unit 10 and some other out-of-order execute unit. Necessarily then, Caulfield fails to teach or suggest that one of out-of-order execute unit might be selected over some alleged other out-of-order execute unit, much less that some instruction might be steered to a particular one such out-of-order execute unit based on such a selection.
Nor does Canal cure the above-described deficiencies of Caulfield. For example, Canal describes a processor architecture comprising a Cluster 1, a Cluster 2, and steering logic which is to decide in which cluster a decoded instruction is to be executed. However, Canal is completely silent as to whether or how (for example) either one of - much less both of - the Cluster 1 or the Cluster 2 might be an out-of-order execution circuit. For at least the foregoing reasons, it would not be possible (much less obvious) to combine the teaching of Caulfield and Canal to somehow practice the features which are variously recited in current independent claims 1, 10 and 16.
Even assuming arguendo that all other claim limitations are taught by Caulfield, Canal, Sheaffer, and Sutanto, which Applicants do not agree, the reference nevertheless fails to either expressly or inherently disclose at least one limitation of Applicants' invention in as complete detail as set forth in the claims, as required by M.P.E.P. §2131. Accordingly, Caulfield, Canal, Sheaffer, and Sutanto fail to anticipate each of independent claims 1, 10 and 16, and any claims depending therefrom. For at least the foregoing reasons, Applicants request that the above rejections of claims 1-9, 16-20 and 22 variously based on Caulfield, Canal, Sheaffer, and Sutanto be withdrawn.”
The examiner respectfully disagrees with the applicant’s assertions above because Canal discloses all limitations of the independent claims as amended. It appears the applicant is in particular arguing that Canal does not disclose the clusters being out-of-order execution circuits and thus cannot disclose steering to one of the out-of-order execution circuits. However, the examiner respectfully disagrees because page 2, section 2 and page 4, Table 2 disclose details of the microarchitecture including the two clusters. In particular the table details that each cluster includes out-of-order instruction issue logic used to issue queued instructions out-of-order for execution. Thus, Canal discloses that each cluster is an out-of-order execution circuit, and therefore discloses steering logic deciding which out-of-order execution cluster to steer instructions too; and the examiner asserts Canal additionally includes all other newly added limitations not argued.
Examiner additionally cites “Exploiting Idle Floating-Point Resources For Integer Execution” as extrinsic evidence as Canal indicates this is the base/conventional architecture upon which Canal extends (see Canal, page 2 section 2: “The target processor microarchitecture is based on the proposal made by Palacharla and Smith [16] and also investigated by Sastry, Palacharla and Smith [18], which extends a conventional microarchitecture in order to allow simple integer and logic instructions to be executed in both clusters.) This reference indicates the architecture is an out-of-order superscalar processor, and thus it is an out-of-order execution processor (see page 120, section 4 and page 127, table 1).
Furthermore, though not used in the current rejections the examiner also directs applicant to the Caufield reference argued above. In particular Fig. 9 uses control circuitry (element 14) to steer instructions to one of an out-of-order execution unit (element 10) or out-of-order execution unit (element 130). The examiner has not used Caulfield in the current rejections because the steering circuitry in this embodiment does not rely upon hard to predict branch sequences. However, the examiner notes that even if applicant would argue that Canal somehow does not disclose out-of-order execution circuits (note the examiner does not concede or agree with this argument), the combination of Canal and Caufield (in light of Fig. 9) would still disclose the argued claim limitations (e.g. modifying a processor including out-of-order issuing clusters as in Canal with a processing including multiple out of order execution units as in Caulfield).
Thus, both Canal and Caufield disclose steering instructions to one of a first or second OOO execution circuit as argued above. (Note: only the rejections regarding Canal have been maintained for additional claim elements added, but not argued in the reply)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
NPL reference “Exploiting Idle Floating-Point Resources for Integer Execution” for teaching out-of-order superscalar processor for dynamically scheduling using partitioning of code using backward branch slices
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183