Prosecution Insights
Last updated: July 17, 2026
Application No. 17/953,213

SURFACE FINISH WITH METAL DOME

Non-Final OA §102§103
Filed
Sep 26, 2022
Examiner
MELLINGER, CORBYN DAVID
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
22 granted / 30 resolved
+5.3% vs TC avg
Strong +44% interview lift
Without
With
+44.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
13 currently pending
Career history
58
Total Applications
across all art units

Statute-Specific Performance

§103
80.9%
+40.9% vs TC avg
§102
9.6%
-30.4% vs TC avg
§112
8.8%
-31.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 30 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group 1 Species A, including claims 1-11 and 19-20 in the reply filed on 30 December 2025 is acknowledged. Claims 12-18 stand as withdrawn. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-5 and 8-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20140069694 (Cho et al). As to Claim 1: Cho teaches a package substrate comprising: a core (Cho Fig 10, 110); a pad over the core (120); a shell around the core (140); a surface finish over the shell (150+160); and a solder resist over the pad, wherein an opening is formed through the solder resist to expose the surface finish (130, opening exposing 160). As to Claim 2: Cho teaches the package substrate of claim 1, wherein a width of the surface finish is greater than a width of the opening formed through the solder resist (150+160 wider than opening in 130). As to Claim 3: Cho teaches the package substrate of claim 1, wherein the shell comprises nickel (140 comprises nickel ¶0060). As to Claim 4: Cho teaches the package substrate of claim 1, wherein the shell is over sidewalls of the pad and over a top surface of the pad (140 over sides and top of 120). As to Claim 5: Cho teaches the package substrate of claim 1, wherein the surface finish comprises palladium and gold (150 and 160 comprise palladium and gold, respectively ¶0060). As to Claim 8: Cho teaches the package substrate of claim 1, wherein the pad is a solder resist defined pad (edge of 130 defines pad). As to Claim 9: Cho teaches the package substrate of claim 1, wherein the pad is a metal defined pad (pad 120 may comprise copper, i.e., is metal-defined ¶0070). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of US 20200343293 (Kawano et al). As to Claim 6: Cho teaches the package substrate of claim 1 but fails to explicitly teach an adhesion promoting layer between the surface finish and the solder resist. Kawano teaches a device having an adhesion promoting layer between a surface finish and an insulating layer (Kawano Fig 1A, 51 between pad 31 and insulator layer 41). It would have been obvious to one of ordinary skill at the time of filing to combine the device of Cho with the adhesion promoting layer of Kawano. Such a layer was known to prevent disconnection of the two layers, which aids in placing solder on the pad of Cho. As to Claim 7: Cho and Kawano teaches the package substrate of claim 6. Kawano, as applied to claim 6, further teaches wherein the adhesion promoting layer comprises silicon and nitrogen (51 comprises silicon and nitrogen ¶0038) Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of US 20220071009 (LeClair). As to Claim 10: Cho teaches the package substrate of claim 1 but fails to explicitly teach wherein the core comprises a borosilicate glass or a fused silica glass. LeClair teaches a device similar to that of Cho having a core comprising a borosilicate glass or a fused silica glass (¶0067). It would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to use a borosilicate glass core since it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill. In re Leshing, 125 USPQ 416 (CCPA 1960) and Sinclair & Carroll Co. v. Interchemical Corp., 65 USPQ 297 (1945). Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of US 20130320457 (Zhang et al). As to Claim 11: Cho teaches the package substrate of claim 1 but fails to explicitly teach wherein the surface finish is deposited with an electrolytic plating process. Zhang teaches a device in which a surface finish may be formed using an electrolytic process (Zhang ¶0025-0026). It would have been obvious to one of ordinary skill in the art at the time of filing to combine the package substrate of Cho with the use of electrolytic plating to form the surface finish. Choice in the use of electrolytic or electroless plating allows greater flexibility for manufacturers to use existing equipment (¶0013) Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho and US 20190304890 (Ecton et al). As to Claim 19: Cho teaches an electronic system comprising: a package substrate, wherein the package substrate comprises: a core (Cho Fig 10, 110); a pad over the core (120); a shell around the core (140); a surface finish over the shell (150+160); a solder resist over the pad, wherein an opening is formed through the solder resist to expose the surface finish (130, opening exposing 160). Cho fails to explicitly teach the package substrate being coupled to a board or a die coupled to the package substrate. Ecton teaches an electronic system in which a package substrate (Ecton Fig 19, 120) is coupled to a board (1670 may connect to a circuit board ¶0064) and a die is coupled to the package substrate (1656). It would have been obvious to combine the teachings of Cho and Ecton at applicant’s time of filing. Such a combination was known and commonly used for connecting IC devices to control boards in computational packages. As to Claim 20: Cho and Ecton teach the electronic system of claim 19. Cho further teaches Cho further teaches wherein the shell comprises nickel, and wherein the surface finish comprises palladium and gold (140, 150, 160 comprise nickel, palladium, and gold respectively ¶0060). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corbyn D Mellinger whose telephone number is (703)756-5683. The examiner can normally be reached M-F 9-6 Eastern. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Corbyn D Mellinger/Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Sep 26, 2022
Application Filed
May 25, 2023
Response after Non-Final Action
Jun 17, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS, INSULATING BASE MEMBERS, WIRINGS, AND AT LEAST ONE WIRING MEMBER
3y 7m to grant Granted Jun 30, 2026
Patent 12648153
SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF FORMATION
3y 4m to grant Granted Jun 02, 2026
Patent 12616060
STACKED RANDOM-ACCESS MEMORY DEVICES WITH REFRIGERATION
4y 2m to grant Granted Apr 28, 2026
Patent 12604760
SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE
3y 5m to grant Granted Apr 14, 2026
Patent 12588490
SEMICONDUCTOR STRUCTURE COMPRISING POWER DELIVER NETWORK STRUCTURE
2y 10m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
99%
With Interview (+44.4%)
3y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 30 resolved cases by this examiner. Grant probability derived from career allowance rate.

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