Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Election/Restriction
This application contains claims 16, 18 and 19 drawn to an invention nonelected with traverse in the reply filed on 7/4/2025. A complete reply to the final rejection must include cancellation of nonelected claims or other appropriate action (37 CFR 1.144) See MPEP § 821.01.
Specification Objection Withdrawal
Applicant’s amendment of the title of the invention is acknowledged. Thus, the objection to specification is withdrawn.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 7, 9, 10 and 12 rejected under 35 U.S.C. 103 as being unpatentable over Chuang (U.S. Patent Pub. No. 2021/0351131) of record, in view of Inokuma (U.S. Patent Pub. No. 2015/0364479) of record, in view of Kwon (KR 20150137224, machine-translation provided).
Regarding Claim 1
FIG. 4 of Chuang discloses a method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate having an active area (AA); the active area comprising a first active area (middle) and a second active area isolated from each other; forming a bitline contact groove (BC) on the semiconductor substrate, the bitline contact groove exposing the first active area; forming an etch stop layer (WA) covering a sidewall of the bitline contact groove, the etch stop layer exposing a partial area of the first active area at a bottom of the bitline contact groove; forming a bitline structure (BL); and forming a conductive plug (CP), the conductive plug being electrically connected to the second active area.
Chuang is silent with respect to “forming an etch stop layer covering a sidewall of the bitline contact groove”; “etching the semiconductor substrate by using the etch stop layer as a mask to form a pit at the bottom of the bitline contact groove, the pit being at least partially positioned in the first active area; removing the etch stop layer”; “a bitline lead of the bitline structure filling up the pit” and “a depth of the bitline contact groove is 3 to 4 times of a depth of the pit”.
Inokuma discloses a similar method for fabricating a semiconductor structure, comprising forming a bitline contact groove (50, FIG. 6) on the semiconductor substrate (10); forming an etch stop layer (52, FIG. 7) covering a sidewall of the bitline contact groove; etching the semiconductor substrate by using the etch stop layer as a mask to form a pit at the bottom of the bitline contact groove (FIG. 8); the pit being at least partially positioned in the first active area; removing the etch stop layer (FIG. 9); a bitline lead of the bitline structure filling up the pit (FIG. 14); forming a conductive plug, the conductive plug being electrically connected to the second active area.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chuang, as taught by Inokuma. The ordinary artisan would have been motivated to modify Chuang in the above manner for purpose of preventing deterioration of a breakdown voltage between conductive regions adjacent to each other ([0003] of Inokuma).
Chuang as modified by Inokuma is silent with respect to “a depth of the bitline contact groove is 3 to 4 times of a depth of the pit”.
However, said ratio is related to the device size and the contact resistance, as evidence by [0038] of Inokuma and the description of Kwon. Said ratio is also related to the parasitic capacitance and the operation speed, as evidenced by the description of KR 102444838. Therefore, said ratio is considered to be a result effective variable where the result is a change in the performance of the semiconductor memory and improvement of the yield, CN 112736080 provides documentary evidence. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Furthermore, Kwon discloses a similar method for fabricating a semiconductor structure, comprising forming a bitline contact groove (25) on the semiconductor substrate (11, FIG. 4), wherein a depth of the bitline contact groove is 3 to 4 times of a depth of the pit.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chuang, as taught by Kwon. The ordinary artisan would have been motivated to modify Chuang in the above manner for purpose of improving the contact resistance between the first impurity region 19 and the first plug (text of Kwon).
Regarding Claim 2
Inokuma discloses forming a first mask layer on the semiconductor substrate, the first mask layer covering the second active area and exposing the first active area; and patterning the semiconductor substrate by using the first mask layer as a mask to form the bitline contact groove exposing the first active area [0044].
Regarding Claim 7
With respect to “an etching rate of the first active area being 10 times more than an etching rate of the etch stop layer”, said ratio is related to the etching efficiency and quality. Therefore, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 9
FIG. 4 of Chuang discloses the semiconductor substrate is buried with a wordline structure [0016], wherein a size of the bitline lead along an extension direction of the wordline structure being a first size, and a depth of the pit being a second size. With respect to “the second size is 0.5 to 2 times of the first size”, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 10
With respect to “under the second etching condition, an etching rate of the etch stop layer being 30 times more than an etching rate of the first active area”, said ratio is related to the etching efficiency and quality. Therefore, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 12
With respect to “the second area is 2 to 4 times of the first area”, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Claims 3 and 6 rejected under 35 U.S.C. 103 as being unpatentable over Chuang, Inokuma and Kwon, in view of Yun (KR 100739532) of record.
Regarding Claim 3
Chuang as modified by Inokuma and Kwon discloses Claim 2.
Chuang as modified by Inokuma and Kwon is silent with respect to “forming an etch stop material layer covering a surface of the first mask layer, the sidewall of the bitline contact groove and the bottom of the bitline contact groove, a part of the etch stop material layer at the bottom of the bitline contact groove being at least partially overlapped with the first active area; and patterning the etch stop material layer to remove the part of the etch stop material layer positioned at the bottom of the bitline contact groove, to form the etch stop layer covering the sidewall of the bitline contact groove”.
FIG. 5 of Yun discloses a similar method for fabricating a semiconductor structure, comprising forming an etch stop material layer (91) covering a surface of the first mask layer (71), the sidewall of the bitline contact groove and the bottom of the bitline contact groove, a part of the etch stop material layer at the bottom of the bitline contact groove being at least partially overlapped with the first active area; and patterning the etch stop material layer to remove the part of the etch stop material layer positioned at the bottom of the bitline contact groove, to form the etch stop layer covering the sidewall of the bitline contact groove.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chuang, as taught by Yun. The ordinary artisan would have been motivated to modify Chuang in the above manner for purpose of obtaining low resistance from the bit line (Abstract of Yun).
Regarding Claim 6
Inokuma discloses the etch stop material layer is patterned by dry etching [0043].
Claims 4 and 5 rejected under 35 U.S.C. 103 as being unpatentable over Chuang, Inokuma, Kwon and Yun, in view of Orimoto (U.S. Patent Pub. No. 2009/0162951) of record.
Regarding Claim 4
Chuang as modified by Inokuma, Kwon and Yun discloses Claim 3.
Chuang as modified by Inokuma, Kwon and Yun is silent with respect to “a material of the etch stop material layer is titanium nitride”.
FIG. 16 of Orimoto discloses a similar method for fabricating a semiconductor structure, wherein a material of the etch stop material layer is titanium nitride [0100].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chuang, as taught by Orimoto. The ordinary artisan would have been motivated to modify Chuang in the above manner for purpose of improving etching selectivity ([0100] of Orimoto).
Regarding Claim 5
Yun discloses the etch stop material layer is formed by atomic layer deposition [0100].
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Chuang, Inokuma and Kwon, in view of Wuzer (U.S. Patent Pub. No. 2003/0113963) of record.
Regarding Claim 8
Chuang as modified by Inokuma and Kwon discloses Claim 7.
Chuang as modified by Inokuma and Kwon is silent with respect to “the first etching condition refers to etching the first active area by using a gas including hydrogen bromide”.
Wuzer discloses a similar method for fabricating a semiconductor structure, wherein the first etching condition refers to etching the first active area by using a gas including hydrogen bromide [0041].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chuang, as taught by Wuzer. The ordinary artisan would have been motivated to modify Chuang in the above manner for purpose of improving etching selectivity ([0041] of Wuzer).
Claim 11 rejected under 35 U.S.C. 103 as being unpatentable over Chuang, Inokuma and Kwon, in view of Wu (U.S. Patent Pub. No. 2004/0000268) of record.
Regarding Claim 11
Chuang as modified by Inokuma and Kwon discloses Claim 10.
Chuang as modified by Inokuma and Kwon is silent with respect to “the second etching condition refers to etching the etch stop layer by using an acid etching liquid including an oxidant”.
Wu discloses a similar method for fabricating a semiconductor structure, wherein the second etching condition refers to etching the etch stop layer by using an acid etching liquid including an oxidant (Claim 90).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chuang, as taught by Wu. The ordinary artisan would have been motivated to modify Chuang in the above manner for purpose of improving etching selectivity ([0045] of Wu).
Claims 13 and 14 rejected under 35 U.S.C. 103 as being unpatentable over Chuang, Inokuma and Kwon, in view of Lin (U.S. Patent Pub. No. 2013/0049085) of record.
Regarding Claim 13
Chuang as modified by Inokuma and Kwon discloses Claim 1, comprising sequentially forming a bitline conductive material layer and a bitline insulation cap material layer covering the filling material layer; patterning the filling material layer, the bitline conductive material layer and the bitline insulation cap material layer to form the bitline lead filling up the pit; and forming an insulation filling layer filling up the bitline contact groove and a bitline insulation layer covering the bitline lead.
Chuang as modified by Inokuma and Kwon is silent with respect to the filling material is “a polysilicon filling material”.
FIG. 1 of Lin discloses a similar method for fabricating a semiconductor structure, wherein the filling material is a polysilicon filling material (Claim 12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chuang, as taught by Lin. The ordinary artisan would have been motivated to modify Chuang in the above manner, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06.
Regarding Claim 14
FIG. 1 of Lin discloses forming a plug hole exposing the second active area; and filling polysilicon into the plug hole to form the conductive plug (Claim 8).
Claim 15 rejected under 35 U.S.C. 103 as being unpatentable over Chuang, Inokuma and Kwon, in view of Jung (U.S. Patent Pub. No. 2015/0028492) of record.
Regarding Claim 15
Chuang as modified by Inokuma and Kwon discloses Claim 1.
Chuang as modified by Inokuma and Kwon is silent with respect to “forming a transfer electrode layer on a side of the conductive plug away from the semiconductor substrate, the transfer electrode layer comprising a plurality of transfer electrodes electrically connected to the conductive plugs in one-to-one correspondence; and forming a device layer on a side of the transfer electrode layer away from the semiconductor substrate, the device layer comprising a plurality of functional devices electrically connected to the plurality of transfer electrodes in one-to-one correspondence”.
FIG. 10 of Jung discloses a similar method for fabricating a semiconductor structure, comprising forming a transfer electrode layer on a side of the conductive plug (168) away from the semiconductor substrate, the transfer electrode layer comprising a plurality of transfer electrodes electrically connected to the conductive plugs in one-to-one correspondence; and forming a device layer (200) on a side of the transfer electrode layer away from the semiconductor substrate, the device layer comprising a plurality of functional devices electrically connected to the plurality of transfer electrodes in one-to-one correspondence.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chuang, as taught by Jung. The ordinary artisan would have been motivated to modify Chuang in the above manner for purpose of forming a memory unit ([0013] of Jung).
Claims 13-15 rejected under 35 U.S.C. 103 as being unpatentable over Chuang, Inokuma and Kwon, in view of Chang (U.S. Patent Pub. No. 2022/0328491) of record.
Regarding Claim 13
Chuang as modified by Inokuma and Kwon discloses Claim 1, comprising sequentially forming a bitline conductive material layer and a bitline insulation cap material layer covering the filling material layer; patterning the filling material layer, the bitline conductive material layer and the bitline insulation cap material layer to form the bitline lead filling up the pit; and forming an insulation filling layer filling up the bitline contact groove and a bitline insulation layer covering the bitline lead.
Chuang as modified by Inokuma and Kwon is silent with respect to the filling material is “a polysilicon filling material”.
FIG. 1 of Chang discloses a similar method for fabricating a semiconductor structure, wherein the filling material is a polysilicon filling material [0048].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chuang, as taught by Chang. The ordinary artisan would have been motivated to modify Chuang in the above manner, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06.
Regarding Claim 14
FIG. 1 of Chang discloses forming a plug hole exposing the second active area; and filling polysilicon into the plug hole to form the conductive plug [0048].
Regarding Claim 15
FIG. 7 of Chang discloses forming a transfer electrode layer on a side of the conductive plug (109) away from the semiconductor substrate, the transfer electrode layer (107) comprising a plurality of transfer electrodes electrically connected to the conductive plugs in one-to-one correspondence; and forming a device layer (capacitor) on a side of the transfer electrode layer away from the semiconductor substrate, the device layer comprising a plurality of functional devices electrically connected to the plurality of transfer electrodes in one-to-one correspondence [0047].
Pertinent Art
KR 20160089095 and KR 102444838 each discloses a depth of the bitline contact groove is 3 to 4 times of a depth of the pit. Pertinent art also includes U.S. Patent Pub. No. 2006/0097304, 2007/0080385 and 2009/0170275.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897