CTFR 17/953,511 CTFR 86224 DETAILED ACTION This office action is in response to amendment filed 5/15/2026. Claims 1-8 and 10-26 are pending. Claim 9 has been canceled. Claim 26 is new. Claims 16-25 have been withdrawn. Claims 1, 3, 7, 8, 10, 12-14, and 16-25 have been amended. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 AIA Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 8 reciting “a palladium between the solder resist layer and the substrate” in combination with claim 1 reciting “an opening in the solder resist layer, wherein a second portion of the substrate surface is a bottom of the opening ” renders the claim indefinite. When palladium seed layer 212 is provided between the solder resist layer and the substrate as shown in FIG. 2B, the solder resist layer 208 is spaced apart from the substrate surface by the seed layer 212. Therefore, an opening that is defined “ in the solder resist layer” as recited in claim 1 would have a ”bottom” that is defined by the bottom of the solder resist layer which is spaced apart from the substrate surface. Therefore, it is unclear how would the “second portion of the substrate surface” form the bottom of the opening in the solder resist layer when a palladium seed layer is provided “between the solder resist layer and the substrate” as recited in claims 1 and 8. Other claims are rejected for depending on a rejected claim. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5, 7, 10-13, 15, and 26 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Karhade et al. US 2021/0391295 A1 (Karhade) . PNG media_image1.png 654 894 media_image1.png Greyscale In re claim 1, Karhade discloses (e.g. FIG. 47 see annotated above) a microelectronics package comprising: a substrate 102 having a substrate surface (top surface); a die 130-1; a solder resist layer 104 (¶ 29) over one or more first portions of the substrate surface (e.g. left/right side portions of the top surface of substrate 102); an opening 120 in the solder resist layer 104 (see highlighted space in layer 104 annotated above), wherein a second portion of the substrate surface (a center portion of top surface of substrate 102, see annotated above) is a bottom of the opening (opening in layer 104 has a bottom that meets the top surface of the center portion of the substrate), and wherein the second portion of the substrate surface is coplanar with the one or more first portions of the substrate surface (coplanar surface portions as indicated by the dashed line in FIG. 47 above); a pad 166 protruding from the substrate surface (solder 166 protruding from the top surface of substrate 102); and a bridge 110 at least partially within the opening 120 in the solder resist layer (space in layer 104) and in between the die 130-1 and the substrate 102, the bridge 110 comprising a via conductively coupled with the pad 180 and the die 130-1 (bridge 110 having conductive pathways including vias to contacts 118 at its top surface and “to other conductive contacts” (¶ 30), such as to contacts 182 at its bottom face (¶ 72)). In re claim 2, Karhade discloses (e.g. FIG. 47) wherein the bridge 110 is not embedded with the solder resist layer 104. In re claim 3, Karhade discloses (e.g. FIG. 47) wherein the bridge 110 is at a distance from the substrate surface (top surface of substrate 102). PNG media_image2.png 595 1087 media_image2.png Greyscale In re claim 4, in a separate interpretation relying on FIG. 56 of Karhade (see annotated FIG. 56 above), Karhade teaches an opening 120 (see highlighted space annotated above) that extends down to contacts 180, the opening 120 is at least partially in the solder resist layer 104 and has a bottom reaching the surface of contact 180. The “substrate” corresponds to the structure from the bottom of 102 to the N-1 layer, wherein a second portion of the substrate surface under the opening 120 is the surface of 180 which is the bottom of the opening 120, and is also coplanar with first portions of the substrate surface defined by the N-1 layer. In this case, Karhade teaches the bridge (including 110+182+106) is spaced above the substrate top surface (surface of 180 and N-1 layer) by a distance corresponding to the thickness of layer 116 which is between 5 microns and 10 microns (¶ 31). In re claim 5, Karhade discloses (e.g. FIG. 47) further comprising a nickel, palladium, gold, or combination thereof layer 116 (layer between 166 and 180) that circumscribes a portion of the pad 166. The bottom portion of the pad 166 is “circumscribed”, in plan view, by the surface finish layer 116 which can be nickel, palladium, and/or gold (¶ 62,195,196). In re claim 7, Karhade discloses (e.g. FIG. 53) wherein the die 130-1 is a first die, the pad (left side solder 166) is a first pad, and the via is a first via (bridge 110 having conductive pathways including vias to contacts 118 at its top surface and “to other conductive contacts” (¶ 30), such as to contacts 182 at its bottom face (¶ 72)), and wherein the microelectronics package further includes: a second die 130-2; and a second pad (right side solder 166); wherein the bridge 110 includes a second via conductively coupled with the second pad (right side solder 166) and the second die 130-2 (bridge 110 having conductive pathways including vias to contacts 118 at its top surface and “to other conductive contacts” (¶ 30), such as to contacts 182 at its bottom face (¶ 72)). In re claim 26, in the separate interpretation relying on FIG. 56 of Karhade (see annotated FIG. 56 above), Karhade teaches an opening 120 (see highlighted space annotated above) that extends down to contacts 180, the opening 120 is at least partially in the solder resist layer 104 and has a bottom reaching the surface of contact 180. The “substrate” corresponds to the structure from the bottom of 102 to the N-1 layer, wherein a second portion of the substrate surface under the opening 120 is the surface of 180 which is the bottom of the opening 120, and is also coplanar with first portions of the substrate surface defined by the N-1 layer. Furthermore, the pad 106 protrudes from the second portion of the substrate surface (surface of 180). PNG media_image3.png 732 1971 media_image3.png Greyscale In re claim 10, Karhade discloses (e.g. FIGs. 53 and 56) a microelectronics package comprising: a substrate 102 having a substrate surface (top surface); first and second dies 130-1,130-2; a solder resist layer 104 (¶ 29) on the substrate surface (top surface of 102), the solder resist layer 104 comprising an opening (see highlighted space in layer 104 annotated above) over a portion of the substrate surface (center portion of the top surface of substrate 102, see FIG. 53 & 56 annotated above); first and second pads (180 in FIG. 53, or solder 106 in FIG. 56) protruding from the portion of substrate surface “at” (understood to mean near) a bottom of the opening (space in 104), wherein the portion of the substrate surface at (near) the bottom of the opening is in a single plane with one or more portions of the substrate under the solder resist layer 104 (portions of substrate 102 under 104 along the plane of the substrate surface at the bottom of the cavity 120, e.g. the portions may be N-1 layers of the substrate under 104); a plurality of pillars 106 comprising a first subset (106 under 130-1) and a second subset (106 under 130-2) extending from the substrate 102 to the first die 130-1 and the second die 130-2, respectively (no specific “pillars” claimed that would structurally distinguish over conductive solders 106); and a bridge 110 at least partially within the opening 120 and in between the substrate 102 and the first and second dies 130-1,130-2, the bridge 110 comprising: a first via conductively coupled with the first pad (left side 180,106 under 110) and the first die 130-1 (bridge 110 having conductive pathways including vias to contacts 118 at its top surface and “to other conductive contacts” (¶ 30), such as to contacts 182 at its bottom face (¶ 72); vias connected to the left side contacts 118 are coupled to die 130-1), and a second via conductively coupled with the second pad (right side 180,106 under 110) and the second die 130-2 (bridge 110 having conductive pathways including vias to contacts 118 at its top surface and “to other conductive contacts” (¶ 30), such as to contacts 182 at its bottom face (¶ 72); vias connected to the right side contacts 118 are coupled to die 130-2). In re claim 11, Karhade discloses (e.g. FIGs. 53 & 56) wherein the bridge 110 is not embedded with the solder resist layer 104. In re claim 12, Karhade discloses (e.g. FIGs. 53 & 56) wherein the bridge 110 is at a distance from the substrate surface (surface at bottom of cavity 120). In re claim 13, Karhade discloses (e.g. FIGs. 53 & 56) further comprising a nickel, palladium, gold, or combination thereof layer 116 (layer between 106 and 180) around (understood to mean nearby) a portion of the first pad (left side 180 or 106) or a portion of the second pad (right side 180 or 106). Surface finish 116 on exposed surface of 180 (¶ 72) is “around” 180 and 106, and surface finish can be nickel, palladium, and/or gold (¶ 62,195,196). In re claim 15, Karhade discloses (e.g. FIG. 53) wherein the first and second vias (bridge 110 having conductive pathways including vias, FIG. 59, ¶ 30) are power vias (¶ 72,97) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karhade as applied to claim 1 above . In re claim 6, Karhade discloses (e.g. FIG. 53) wherein the bridge 110 has a thickness between 30 microns and 200 microns (¶ 31). The claimed thickness from about 35 microns to about 70 microns is overlapped and within the range disclosed by Karhade. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the bridge 110 with a thickness from about 35 microns to about 70 microns based on desired functionality and overall device size. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). See MPEP 2144.05 . 07-22-aia AIA Claim s 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Karhade as applied to claim s 1 and 10 above, and further in view of Liu et al. US 2014/0353827 A1 (Liu) . In re claims 8 and 14, Karhade discloses the claimed invention including the solder resist layer 104 above the substrate 102, and contacts 114 between the top surface of the substrate 102 and solder resist layer 104. Karhade does not explicitly disclose palladium between the solder resist layer 104 and the substrate 102. However, Liu teaches a package substrate 150 comprising contacts 135 on the top surface of the substrate 150, wherein the contacts are formed by (FIGs. 3-8) providing a seed layer 330,610 coating the via holes 332,604 followed by forming plating to form contacts 410,620, wherein the seed layer 330,610 include palladium seed (¶ 44,51). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a palladium seed under Karhade’s contacts 114 to enhance the plating layer as is well-known in the art. As such, a palladium seed under the contacts 114 is located between the solder resist layer 104 and the remainder of the substrate 102. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960) . Response to Arguments 07-37 AIA Applicant's arguments filed 5/15/2026 have been fully considered but they are not persuasive. The amended claim limitations are taught by Karhade under various new interpretations as applied above. More specifically, as shown FIG. 47 applied to claim 1 above, the claimed “opening in the solder resist layer” may correspond only to the space in solder resist layer 104 and the bottom of the opening in the solder resist layer 104 is a center (second) portion of the top surface of the substrate which is also coplanar with side (first) portions of the top surface of the substrate as shown in FIG. 47 annotated above. Additionally, as shown in FIG. 56 applied to claims 4 and 26, the opening may correspond to the entirely of the cavity 120 extending to surface of 180 which defines the second portion of the substrate surface, and which is coplanar with first portions of the substrate surface defined by the N-1 layers. Furthermore, claim 10 reciting “at a bottom of the opening” is understood to mean “near a bottom of the opening”. As such, the portion of the recessed substrate surface below the cavity 120 is “at” or “near” the bottom of the opening that is defined in the solder resist layer 104. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896 Application/Control Number: 17/953,511 Page 2 Art Unit: 2896 Application/Control Number: 17/953,511 Page 3 Art Unit: 2896 Application/Control Number: 17/953,511 Page 4 Art Unit: 2896 Application/Control Number: 17/953,511 Page 5 Art Unit: 2896 Application/Control Number: 17/953,511 Page 6 Art Unit: 2896 Application/Control Number: 17/953,511 Page 7 Art Unit: 2896 Application/Control Number: 17/953,511 Page 8 Art Unit: 2896
Prosecution Insights