Prosecution Insights
Last updated: April 19, 2026
Application No. 17/953,648

STACKED PEROVSKITE FERROELECTRIC FIELD EFFECT TRANSISTOR (FEFET) DEVICES

Non-Final OA §112
Filed
Sep 27, 2022
Examiner
RAHMAN, MOHAMMAD A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
98%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
459 granted / 531 resolved
+18.4% vs TC avg
Moderate +12% lift
Without
With
+11.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
27 currently pending
Career history
558
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
31.1%
-8.9% vs TC avg
§112
18.9%
-21.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 531 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/ Restrictions Applicant's election of group II without traverse: claims 1-21 cancellation of claims 22-25 and submission of new claims 26-29, in the “Response to Election / Restriction Filed - 12/18/2025” is/are acknowledged. This office action considers claims 1-21, 26-29, in “Claims - 12/18/2025”, pending for prosecution. Claim Rejections - 35 USC § 112 The following is a quotation of the second paragraph of 35 U.S.C. 112: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-21 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites: “dielectric materials between the source/drain metals and the perovskite gate materials”. There is insufficient antecedent basis for this limitation in the claim. Claims 2-11 depend from claim 1. Claim 12 recites: “one or more interconnect layers, the interconnect layers electrically connecting the transistors; wherein the stacked transistors each include:”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection: “one or more interconnect layers, the one or more interconnect layers electrically connecting the plurality of stacked transistors; wherein the plurality of stacked transistors each include:”. Claim 12 further recites: “dielectric materials between the source/drain metals and the perovskite gate materials”. There is insufficient antecedent basis for this limitation in the claim. Claims 13-21 depend from claim 12. REASON FOR ALLOWANCE Claims 26-29 are allowed over prior art. The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14). Regarding claim 26, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation). The most relevant prior art reference(s) (US 20200212194 A1 to Gosavi) substantially teach(es) some of limitations in claim 26 as indicated below: an integrated circuit component comprising a plurality of transistor devices (Fig. 2 shows a plurality of tri-gate transistors – [0084]), each transistor device (see Fig. 1A for an individual tri-gate transistor) comprising: a first perovskite semiconductor region (channel – see [0060]. Figs. 1C and 1D and ([0071]-[0072]) teach that conductive layers 131, 141 [channel used to form the transistor] perovskite material); first perovskite ferroelectric regions (106 – [006] – “FE material 106 (e.g., FE dielectric)”) adjacent the first perovskite semiconductor region (channel); first perovskite gate regions (107 – [0069] teaches 107 can be strontium titanium oxide [SrTiO3] which is an example of a perovskite material according to [0011] of the applicant’s specification) adjacent the first perovskite ferroelectric regions (106), but not the limitations of “a second perovskite semiconductor region; second perovskite ferroelectric regions adjacent the second perovskite semiconductor region; second perovskite gate regions adjacent the second perovskite ferroelectric regions, wherein the second perovskite gate regions comprise one of the first perovskite gate regions; a first source/drain region adjacent a first side of the first perovskite semiconductor region and the second perovskite semiconductor region; a second source/drain region adjacent a second side of the first perovskite semiconductor region and the second perovskite semiconductor region.” as recited in claim 26. Therefore, the claim 26 is deemed patentable over the prior art. Regarding claims 27-29, they are allowed due to their dependencies on claim 26. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD A RAHMAN/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Sep 27, 2022
Application Filed
Apr 21, 2023
Response after Non-Final Action
Feb 13, 2026
Non-Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
98%
With Interview (+11.7%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 531 resolved cases by this examiner. Grant probability derived from career allow rate.

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