DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/23/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 14, 16 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsueh et al. (PG Pub. No. US 2020/0006334 A1).
Regarding claim 1, Hsueh teaches an integrated circuit (100) comprising:
a first semiconductor device (¶¶ 0014-0015: 1st device region of fig. 19, equivalent to device 30 of fig. 1) having a first semiconductor region (¶ 0020: strips 60 and/or fins 64) extending in a first direction (fin-extending direction, e.g. A-A cutline of fig. 1) from a first source region to a first drain region (¶¶ 0029, 0031 & fig. 8A: 64 extends between pair of 65/80), and a first gate structure (¶ 0035: gate 97 in 1st device region) extending in a second direction (fig. 19: gate-extending direction, e.g. B-B cutline) over the first semiconductor region (figs. 11A-11C: 97 extends over 1st device region);
a second semiconductor device (2nd device region of fig. 19) having a second semiconductor region (2nd strips/fins 60/64) extending in the first direction from a second source region to a second drain region (fig. 8A: 2nd 60/64 extends between 2nd pair of 65/80), and a second gate structure (fig. 19: 97 in 2nd device region) extending in the second direction over the second semiconductor region (figs. 11A-11C, 19: 97 extends in B-B direction of 2nd device region); and
a gate cut (¶ 0054: dielectric 140, formed in opening 141) between and separating the first gate structure and the second gate structure (figs. 17A, 19: 140/141 arranged between gates 97 in 1st and 2nd device regions), the gate cut comprising a dielectric material (¶ 0054: 140 comprises dielectric material) and having a height-to-width aspect ratio of at least 8:1 (¶ 0053: 141 has a height-to-width aspect ratio of 18:1).
Regarding claim 2, Hsueh teaches the integrated circuit of claim 1, wherein the gate cut has a height greater than 150 nm (¶ 0053: Depth D1=150nm to 250 nm), and height-to-width aspect ratio of at least 10:1 (¶ 0053: 18:1).
Regarding claim 3, Hsueh teaches the integrated circuit of claim 1, wherein the gate cut has a height between about 150 nm and about 180 nm (¶ 0053).
Regarding claim 6, Hsueh teaches the integrated circuit of claim 1, wherein the gate cut has a first width at a top surface of the first gate structure and the second gate structure (¶ 0053 & fig. 14A: width W5 of the etched opening 141 near the top of the metal gates 97), and a second width at a bottom surface of the first gate structure and the second gate structure (¶ 0053 & fig. 14A: width W6 of the etched opening 141 near the bottom of gates 97), the first width being at most 10% greater than the second width (¶ 0053 & fig. 14A: in at least one embodiment, W5 at top of 97 equal to W6 at bottom of 97, which lies within the claimed range of “at most 10% greater”).
Regarding claim 14, Hsueh teaches an integrated circuit comprising:
a first semiconductor device (¶¶ 0014-0015: 1st device region of fig. 19, equivalent to device 30 of fig. 1) having a first semiconductor region (¶ 0020: strips 60 and/or fins 64) extending in a first direction (fin-extending direction, e.g. A-A cutline of fig. 1) from a first source region to a first drain region (¶¶ 0029, 0031 & fig. 8A: 64 extends between pair of 65/80), and a first gate structure (¶ 0035: gate 97 in 1st device region) extending in a second direction (fig. 19: gate-extending direction, e.g. B-B cutline) over the first semiconductor region (figs. 11A-11C: 97 extends over 1st device region);
a second semiconductor device (2nd device region of fig. 19) having a second semiconductor region (2nd strips/fins 60/64) extending in the first direction from a second source region to a second drain region (fig. 8A: 2nd 60/64 extends between 2nd pair of 65/80), and a second gate structure (fig. 19: 97 in 2nd device region) extending in the second direction over the second semiconductor region (figs. 11A-11C, 19: 97 extends in B-B direction of 2nd device region); and
a gate cut (¶ 0054: dielectric 140, formed in opening 141) between and separating the first gate structure and the second gate structure (figs. 17A, 19: 140/141 arranged between gates 97 in 1st and 2nd device regions), the gate cut comprising a dielectric material (¶ 0054: 140 comprises dielectric material) and having less than 2 nm of sidewall taper between a top surface of the first gate structure and the second gate structure and a bottom surface of the first gate structure and the second gate structure (¶ 0053 & fig. 14A: in at least one embodiment, W5 at top of gates 97 equal to W6 at bottom of gates 97, which meets the broadest reasonable interpretation of “having less than 2 nm of sidewall taper”).
Regarding claim 16, Hsueh teaches the integrated circuit of claim 14, wherein the first gate structure includes a first gate dielectric (¶ 0038 & fig. 19: portion of 96 in 1st device region) around the first semiconductor region (fig. 19: 96 disposed around 60/64 in 1st device region), and the second gate structure includes a second gate dielectric (fig. 19: portion of 96 in 2nd device region) around the second semiconductor region (fig. 19: 96 disposed around 60/64 in 2nd device region).
Regarding claim 18, Hsueh teaches the integrated circuit of claim 14, wherein the gate cut has a height-to-width aspect ratio of at least 5:1 (¶ 0053: opening 141 has a D1:W5 aspect ratio greater than 5:1).
Regarding claim 19, Hsueh teaches the integrated circuit of claim 14, wherein the gate cut has a first width at the top surface of the first gate structure and the second gate structure (¶ 0053 & fig. 14A: width W5 at top surface of gates 97), and a second width at the bottom surface of the first gate structure and the second gate structure (¶ 0053 & fig. 14A: width W6 at bottom surface of gates 97), the first width being at most 10% greater than the second width (¶ 0053: in at least one embodiment, W5-W6, which lies inside the claimed range of “at most 10%”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hsueh as applied to claims 1 and 14 above, and further in view of Wu et al. (PG Pub. No. US 2023/0015372 A1).
Regarding claims 4 and 15, Hsueh teaches the integrated circuits of claims 1 and 14, comprising 1st and 2nd semiconductor regions (fig. 19 among others: 60/64 in 1st and 2nd device regions).
Hsueh does not teach wherein the first semiconductor region comprises a plurality of first semiconductor nanoribbons and the second semiconductor region comprises a plurality of second semiconductor nanoribbons.
Wu teaches an integrated circuit (¶ 0014: 200), wherein a first semiconductor region (¶ 0018: 204A, including multilayer structure ML) comprises a plurality of first semiconductor nanoribbons (¶ 0018, figs. 9B-9C: portion ML includes channel layers 206) and a second semiconductor region (¶ 0018: 204B/ML) comprises a plurality of second semiconductor nanoribbons (figs. 9B-9C: 204B includes channel layers 206).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the 1st and 2nd semiconductor regions of Hsueh with nanoribbons, as a means to improve electrostatic control of the channel regions, improving device performance.
Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hsueh as applied to claims 1 and 16 above, and further in view of Zhou et al. (PG Pub. No. US 2023/0139399 A1).
Regarding claims 5 and 17, Hsueh teaches the integrated circuits of claims 1 and 16, wherein the first gate structure includes a first gate dielectric (¶ 0038 & fig. 19: portion of 96 in 1st device region) around the first semiconductor region (fig. 19: 96 disposed around 60/64 in 1st device region), and the second gate structure includes a second gate dielectric (fig. 19: portion of 96 in 2nd device region) around the second semiconductor region (fig. 19: 96 disposed around 60/64 in 2nd device region).
Hsueh does not teach wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of the gate cut.
Zhou teaches an integrated circuit (¶ 0081 & figs. 13-14: 200), wherein a first gate structure (¶ 0100: replacement gate including conductor 150 and dielectric 152) includes a first gate dielectric (152) around a first semiconductor region (¶ 0095 & fig. 13: 152 disposed around nanosheets 210 in region 203), and a second gate structure (¶ 0100, 0129: replacement gate conductor 154 and dielectric 156) includes a second gate dielectric (156) around a second semiconductor region (¶ 0095 & fig. 13: 156 disposed around nanosheets 214 in region 205), wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of a gate cut (fig. 13: 152 and 156 not present on sidewall of gate cut 180).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the gate dielectric of Hsueh similar to that of Zhou, as a means to apply a tensile force to the gate structures (Zhou, ¶ 0002), improving mobility of minority carriers (Zhou, ¶ 0057) and corresponding device performance.
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsueh as applied to claims 1 and 14 above, and further in view of Wei et al. (PG Pub. No. US 2021/0280708 A1).
Regarding claims 7 and 20, Hsueh teaches the integrated circuits of claims 1 and 14.
Hsueh fails to teach a printed circuit board comprising the integrated circuits of claims 1 and 14.
Wei teaches a printed circuit board comprising integrated circuits (¶¶ 0017, 0108-0109 & figs. 10-11: 2303 comprises integrated circuits similar to that of Hsueh).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure a printed circuit board with the integrated circuits of Hsueh, as a means to provide a memory device (e.g., a DRAM or an SRAM device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element (Wei, ¶ 0099).
Conclusion
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/BRIAN TURNER/ Examiner, Art Unit 2818