DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention Group I and Species I (FIG. 2) and Subspecies A (claim 4), encompassing claims 1-4, 6-7, 9-11, and 17-21, in the reply filed on 12/15/2025 is acknowledged.
Claims 5, 8 and 12-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/15/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-7, 9-11 and 17-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
The term “proximate” in claim 1 is a relative term which renders the claim indefinite. The term “proximate” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear the degree of proximity that is required to be considered “proximate”.
Claim 17 reciting “the grounding members partially extending into a bulk semiconductor region” renders the claim indefinite. It is unclear if the intended scope is to recite that only some (partial) of the grounding members are extending into the bulk semiconductor region, or that each of the grounding members has a partial extent into the bulk semiconductor region.
Claim 18 reciting “the grounding members extend into a barrier metal embedded in the bulk semiconductor region adjacent the first and second sides” renders the claim indefinite. It is unclear if the plural “grounding members” extend into a common barrier metal or does each one of the grounding member extends into a corresponding barrier metal. Furthermore, if is unclear if the same barrier metal is adjacent both the first and second sides. Or is the barrier metal adjacent one of the first and second sides. Furthermore, it is unclear how does the grounding members extend into a barrier metal. As best understood, the grounding member and the barrier metal do not intermix. As such, in the spaces where the grounding members exist, the barrier metal does not exist. Therefore, it is unclear what constitutes “into a barrier metal”.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 9-11, 17 and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koester et al. US 2011/0233785 A1 (Koester).
PNG
media_image1.png
722
1126
media_image1.png
Greyscale
In re claim 1, as best understood, Koester discloses (e.g. FIG. 9) a semiconductor die comprising:
a semiconductor substrate 10 (¶ 26);
metal interconnects 92 proximate a first (top) side of the semiconductor substrate 10;
a metal contact 62 proximate a second (bottom) side of the semiconductor substrate opposite the first side;
a first grounding member 70 extending from a grounding interconnect of the metal interconnects 92 (grounded 70 and 98, ¶ 50,51) to a first distal point (may be any point in the substrate 10 to which 70 extends, e.g. 70 extends from the top of substrate 10 to various points along the vertical extent of 70 until the bottom surface of 70, see annotated FIG. 9 above) in the semiconductor substrate; and
a second grounding member 50 extending from the metal contact 62 to a second distal point (e.g. to a point below 70 where 50 extends, see annotated FIG. 9 above) in the semiconductor substrate, the first distal point (e.g. a point along 70) closer to the first (top) side of the semiconductor substrate than the second distal point (e.g. a point along 50 below 70) is to the first (top) side of the semiconductor substrate.
In re claim 2, Koester discloses (e.g. FIG. 9) wherein the first and second grounding members 70,50 extend into the semiconductor substrate 10 by at least 0.5 microns and up to 1 micron (50 extends entirely through, while trench 69 of structure 70 extends 30 microns to 600 microns, ¶ 29). The limitation “extend by … at least 0.5 microns and up to 1 micron” is understood to recite a lower limit. As such, each of 50 and 70 meets “extend into the substrate by “at least 0.5 microns and up to 1 micron”. E.g. 30 microns encompasses “extends by at least 0.5 microns and up to 1 micron”.
In re claim 4, Koester discloses (e.g. FIG. 9) wherein at least one of the first grounding member 70 or the second grounding member 50 includes a pillar. No specific “pillar” structure has been claimed that would distinguish over either extending structures 50 or 70.
In re claim 9, Koester discloses (e.g. FIG. 9) wherein the first grounding member 70 is included in a first plurality of first grounding members 70 extending into the first side of the semiconductor substrate and the second grounding member 50 is included in a second plurality of second grounding members extending into the second side of the semiconductor substrate, a first number of members in the first plurality of first grounding members 70 greater than a second number of members in the second plurality of second grounding members 50 (see FIG. 9, more 70 than 50 in substrate 10).
In re claim 10, Koester discloses (e.g. FIG. 9) wherein the metal contact 62 is coupled to a through-silicon via (TSV) 50 (another one of 50) extending between the first (top) side and the second (bottom) side of the semiconductor substrate 10, the first and second grounding members 70,50 electrically coupled to the TSV (¶ 50-52).
In re claim 11, Koester discloses (e.g. FIG. 9) wherein the second grounding member 50 extends through an isolation layer 20,40 (¶ 25,28) between the second (bottom) side of the semiconductor substrate 10 and the metal contact 62.
In re claim 17, as best understood, Koester discloses (e.g. FIG. 9) an integrated circuit (IC) package comprising:
a first die 4;
a second die 2 including a through-silicon via (TSV) 50 extending between first (bottom) and second (top) sides of the second die 2, the first die 4 stacked on the first (bottom) side of the second die 2, the TSV 50 electrically coupled to the first die 4 (¶ 59);
a metal contact 92 on the second (top) side of the second die 2 and electrically coupled to the TSV 50 (¶ 50,52, e.g. grounded); and
grounding members (including 70 and other ones of 50) adjacent the first and second sides of the second die 2, the grounding members 70,50 “partially extending into a bulk semiconductor region 10 of the second die 2” (50 extending entirely through substrate 10 encompasses “partially”), a first one of the grounding members 70 extending from the metal contact 92.
In re claim 19, Koester discloses (e.g. FIG. 9) including metal interconnects 62 adjacent the first (bottom) side, a second one of the grounding members (another one of 50) extending from a grounding interconnect 62 of the metal interconnects.
In re claim 20, Koester discloses (e.g. FIG. 9) including one or more transistors (¶ 27) in a device layer 32 between the first (bottom) side of the bulk semiconductor region 10 and the metal interconnects 62, the second one of the grounding members (the other one of 50) to extend through the device layer 32.
In re claim 21, Koester discloses (e.g. FIG. 9) wherein a portion of the grounding members (e.g. 70) extending into the bulk semiconductor region 10 is not electrically isolated from the bulk semiconductor region 10 (where 71 is optional, ¶ 43).
Claims 1, 4, 6-7, 9-11 and 17-21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kuo et al. US 2023/0378026 A1 (Kuo).
PNG
media_image2.png
696
1230
media_image2.png
Greyscale
In re claim 1, as best understood, Kuo discloses (e.g. 2A-2B) discloses a semiconductor die comprising:
a semiconductor substrate 100;
metal interconnects Mn proximate a first (top) side of the semiconductor substrate;
a metal contact 248 proximate a second (bottom) side of the semiconductor substrate 100 opposite the first (top) side;
a first grounding member 122+118 (¶ 26) extending from a grounding interconnect Mn of the metal interconnects to a first distal point (may be any point in the substrate 100 to which 118 extends, e.g. 118 extends to various points along the vertical extent of 118 in substrate 100 until the bottom surface of 118, see annotated FIG. 2B above) in the semiconductor substrate; and
a second grounding member 238 (¶ 47) extending from the metal contact 248 to a second distal point (e.g. a point below 118 where 238 extends, see annotated FIG. 2B above) in the semiconductor substrate, the first distal point (e.g. a point along 118 in substrate 100) closer to the first (top) side of the semiconductor substrate than the second distal point (e.g. a point along 238 below 118) is to the first (top) side of the semiconductor substrate.
In re claim 4, Kuo discloses (e.g. FIG. 2B) wherein at least one of the first grounding member 122,118 or the second grounding member 238 includes a pillar. No specific “pillar” structure has been claimed that would distinguish over either extending structures 118,122,238.
In re claim 6, Kuo discloses (e.g. FIG. 2 & 4) including a barrier metal (titanium nitride layer, ¶ 54) in the semiconductor substrate 100 to envelop a portion of at least one of the first grounding member or the second grounding member (core conductor, ¶ 54).
In re claim 7, Kuo discloses (e.g. FIGs. 2 & 4) wherein the barrier metal includes at least one of tantalum or titanium (¶ 54).
In re claim 9, Kuo discloses (e.g. FIG. 2A) wherein the first grounding member 118 is included in a first plurality of first grounding members 118+122 (e.g. all four of 118+122 as shown in FIG. 2A) extending into the first (top) side of the semiconductor substrate 100 and the second grounding member 238 is included in a second plurality of second grounding members (e.g. only two of 238 in FIG. 2A) extending into the second (bottom) side of the semiconductor substrate, a first number of members (e.g. four) in the first plurality of first grounding members 118+122 greater than a second number of members (e.g. two) in the second plurality of second grounding members 238.
In re claim 10, Kuo discloses (e.g. FIG. 2A) wherein the metal contact 248 is coupled to a through-silicon via (TSV) (one of 122+118+238) extending between the first (top) side and the second (bottom) side of the semiconductor substrate 100, the first and second grounding members (other ones of 118,122,238) electrically coupled to the TSV.
In re claim 11, Kuo discloses (e.g. FIG. 2A) wherein the second grounding member 238 extends through an isolation layer 246,250 between the second (bottom) side of the semiconductor substrate 100 and the metal contact 248.
In re claim 17, as best understood, Kuo discloses (e.g. FIGs. 2A & 2B) an integrated circuit (IC) package comprising:
a first die SD2;
a second die SD1 including a through-silicon via (TSV) (one of 122+118+238) extending between first (top) and second (bottom) sides of the second die SD1, the first die SD2 stacked on the first (top) side of the second die SD1, the TSV 122+118+238 electrically coupled to the first die SD2 (through metallization Mn);
a metal contact 248 on the second (bottom) side of the second die SD1 and electrically coupled to the TSV 122+118+238; and
grounding members (other ones of 118,122,238, ¶ 26,47) adjacent the first and second sides of the second die SD1, the grounding members 118,122,238 “partially extending into a bulk semiconductor region” 100 of the second die SD1, a first one of the grounding members extending 238 from the metal contact 248.
In re claim 18, Kuo discloses (e.g. FIG. 2 & 4) wherein “the grounding members extend into a barrier metal (titanium nitride layer, ¶ 54) embedded in the bulk semiconductor region 100 adjacent the first and second sides”. No proximity claimed that would distinguish over Kuo’s adhesion layer that is considered to be “adjacent” to the top and bottom sides.
In re claim 19, Kuo discloses (e.g. FIG. 2B) including metal interconnects Mn adjacent the first (top) side, a second one of the grounding members 118+122 extending from a grounding interconnect Mn of the metal interconnects (¶ 26,47).
In re claim 20, Kuo discloses (e.g. FIGs. 2A & 2B) including one or more transistors in a device layer CS1,116,FN (¶ 47) between the first (top) side of the bulk semiconductor region 100 and the metal interconnects Mn, the second one of the grounding members 118+122 to extend through the device layer CS1,116,FN.
In re claim 21, Kuo discloses (e.g. FIGs. 2A & 2B) wherein a portion of the grounding members 122,118,238 extending into the bulk semiconductor region 100 is not electrically isolated from the bulk semiconductor region (the circuits of the IC are considered all electrically connected, either directly or indirectly; therefore, the grounding members 122,118,238 are not electrically isolated from various parts of the substrate 100 that all form part of the electrically connected circuit).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koester as applied to claim 1 above.
In re claim 3, Koester discloses (e.g. FIG. 9) wherein a width of the first grounding member 70 is 0.5 micron to 10 microns in trench 69 is where 71 is optional, ¶ 42-43, and the second grounding member 50 has a width of 0.5 micron to 10 microns (trench 49 for structure 50, ¶ 29). The claimed range of between 0.7 microns and 1.2 microns is obvious over Koester teaching overlapping widths. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). See MPEP 2144.05. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the grounding members 50,70 to desired width for optimizing feature density while minimizing crosstalk.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896