DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 24, 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3 have been considered but are moot on ground of new rejection and interpretation of the current prior art of record.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. (Muramatsu) (JP 2017220490A) in view of SUEHIRO et al. (SUEHIRO) (US 2010/0123164 A1) as evidenced by Lee et al. (Lee) (US 2017/0005075 A1).
In regards to claim 1, Muramatsu (Figs. 29, 30 and associated text) discloses a semiconductor device (Figs. 29, 30), comprising: an insulated circuit board (item 10) including a conductive pattern layer (item 12); a conductive sintered member (items 20, 25) disposed on the conductive pattern layer, the conductive sinter member (items 20, 25) having a frame (items 25t, 25s, 22, 21) formed on a surface thereof opposite to the conductive pattern layer (item 12), to thereby form a recess (shown but not labeled) on the surface, the frame (items 25t, 22) shaping an outer edge of the recess (shown but not labeled); a semiconductor chip (item 30) having a top face (where item 33 resides), a bottom face (where item 32 resides) opposite to the top face (where item 33 resides), and a lateral face (lateral face of item 30 on the left and right), the semiconductor chip (item 30) being mounted in the recess (shown but not labeled) of the conductive sintered member (items 20, 25) with the bottom face (where item 32 resides) opposing the recess (shown but not labeled), the bottom face (where item 32 resides) being located closer to the conductive pattern layer (item 12) than a top end (uppermost surface of items 25t and 22) of the frame (items 25, 22), but does not specifically disclose the top face being located closer to the conductive pattern layer than a top end of the frame; and a coating material covering the semiconductor chip mounted in the recess of the conductive sintered member.
SUEHIRO (Figs. 1, 5, 6, 10 and associated text and equivalent items) discloses the top face (top face of item 21) being located closer to the conductive pattern layer (items 3, 43, 43a, 41, 41 plus 43, 41 plus 43a, 41 plus 43 plus 3 or 41 plus 43a plus 3) than a top end of the frame (items 22, which can be made of sintered material as well, paragraph 130); and a coating material (item 24) covering the semiconductor chip (item 21) mounted in the recess of the conductive sintered member (item 22, paragraph 130, sintered material).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of SUEHIRO for the purpose of connecting electrically and/or mechanically and thermal conductivity (paragraph 91, 130).
As evidenced by Lee (Figs. 1A-1D, 7A, 7B and associated text), a bonding member (item 140, AS, ASa plus ASaw, Asa plus ASae) can have a portion (items ASaw or ASae) having an top end (uppermost surface of items ASae or ASaw) that is higher than the top surface of chip/die (item 120) and physically contacts the lateral surface of the chip/die (item 120)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Lee for the purpose of protection and a mechanical bond since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 2, Muramatsu (Figs. 29, 30 and associated text) as modified by SUEHIRO (Figs. 1, 5, 6, 10 and associated text and equivalent items) and Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: the coating material (item 24, SUEHIRO, item 108, Lee) covers the top face, the lateral face, and a corner portion between the top face and the lateral face, of the semiconductor chip (item 30, Muramatsu, item 21, SUEHIRO) mounted in the recess (shown but not labeled, Muramatsu and SUEHIRO) of the conductive sintered member (items 20, 25, Muramatsu, item 22, SUEHRO).
In regards to claim 3, Muramatsu (Figs. 29, 30 and associated text) as modified by SUEHIRO (Figs. 1, 5, 6, 10 and associated text and equivalent items) and Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: porosity of the conductive sintered member (items 20, 25, Muramatsu, item 22, SUEHIRO) between the recess (shown but not labeled, Muramatsu) and the conductive pattern layer (item 12, Muramatsu, items 3, 43, 43a, 41, 41 plus 43, 41 plus 43a, 41 plus 43 plus 3 or 41 plus 43a plus 3, SUEHIRO) is lower than porosity of the frame (items 25t, 22, Muramatsu, item 22, SUEHIRO) in a cross-sectional view. Examiner notes that the sintered body of Muramatsu share the same materials and heating temperature range of the Applicant and would thus share the same characteristics.
In regards to claim 14, Muramatsu (Figs. 29, 30 and associated text) as modified by SUEHIRO (Figs. 1, 5, 6, 10 and associated text and equivalent items) and Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: the frame (items 25t, 25s, 22, 21, Muramatsu, item 22, SUEHIRO) and the semiconductor chip (item 30, Muramatsu, item 21, SUEHIRO) form a filling space (shown but not labeled, Muramatsu and SUEHRIO) that is a space surrounded by the frame (items 25t, 25s, 22, 21, Muramatsu, item 22, SUEHIRO) and, in a thickness direction of the semiconductor chip (item 30, Muramatsu, item 21, SUEHIRO), between the top end of the frame (items 25t, 25s, 22, 21, Muramatsu, item 22, SUEHIRO) and the top face of the semiconductor chip (item 30, Muramatsu, item 21, SUEHIRO); and the coating material (item 24, SUEHIRO) fully fills the filling space (shown but not labeled, Muramatsu and SUEHRIO).
Claim(s) 1-3 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. (Muramatsu) (JP 2017220490A) in view of SUEHIRO et al. (SUEHIRO) (US 2010/0123164 A1) as evidence by or in view of Koike et al. (Koike) (US 2021/0066234 A1) and/or Hwang et al. (Hwang) (US 2021/0151410 A1) as evidenced by Lee et al. (Lee) (US 2017/0005075 A1).
In regards to claim 1, Muramatsu (Figs. 29, 30 and associated text) discloses a semiconductor device (Figs. 29, 30), comprising: an insulated circuit board (item 10) including a conductive pattern layer (item 12); a sintered member (items 20, 25) disposed on the conductive pattern layer, the sinter member (items 20, 25) having a frame (items 25t, 25s, 22, 21) formed on a surface thereof opposite to the conductive pattern layer (item 12), to thereby form a recess (shown but not labeled) on the surface, the frame (items 25t, 22) shaping an outer edge of the recess (shown but not labeled); a semiconductor chip (item 30) having a top face (where item 33 resides), a bottom face (where item 32 resides) opposite to the top face (where item 33 resides), and a lateral face (lateral face of item 30 on the left and right), the semiconductor chip (item 30) being mounted in the recess (shown but not labeled) with the bottom face (where item 32 resides) opposing the recess (shown but not labeled), the bottom face (where item 32 resides) being located closer to the conductive pattern layer (item 12) than a top end (uppermost surface of items 25t and 22) of the frame (items 25, 22), but does not specifically disclose the top face being located closer to the conductive pattern layer than a top end of the frame; and a coating material covering the semiconductor chip mounted in the recess of the conductive sintered member.
SUEHIRO (Figs. 1, 5, 6, 10 and associated text and equivalent items) discloses the top face (top face of item 21) being located closer to the conductive pattern layer (items 3, 43, 43a, 41, 41 plus 43, 41 plus 43a, 41 plus 43 plus 3 or 41 plus 43a plus 3) than a top end of the frame (items 22, which can be made of sintered material as well, paragraph 130); and a coating material (item 24) covering the semiconductor chip (item 21) mounted in the recess of the conductive sintered member (item 22, paragraph 130, sintered material).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of SUEHIRO for the purpose of connecting electrically and/or mechanically and thermal conductivity (paragraph 91, 130).
As evidenced by Koike (Fig. 1A, 1B and associated text) teaches sinter/bonding member (item 30, paragraph 19) having a frame (items 32, 34), the frame (items 32, 34) shaping an outer edge of recess (shown but not labeled) can have a second portion (item 34) that is higher or lower than the first portion (item 32, paragraphs 23-25) as long as the angle q satisfies the condition of 80 degrees or less. Examiner notes Koike does not disclose any height restrictions, therefore even though it might not be shown in the figures, the height of the top end (uppermost surface of item 34) of the second portion (item 34) can be higher than the top surface of the semiconductor chip/die (item 20) if so desired.
As evidenced by Hwang (Figs. 12-14 and associated text), a bonding member (items 540, 540a or 640) that has portion (portion surrounding lateral surfaces of the chip/die 120) having an top end (uppermost surface of items 540, 540a or 640) that is even, lower than or higher than the top surface of chip/die (item 120).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate teachings of Koike or Hwang for the purpose mechanical and/or electrical bond, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
As evidenced by Lee (Figs. 1A-1D, 7A, 7B and associated text), bonding member (item 140, AS, ASa plus ASaw, Asa plus ASae) can have a portion (items ASaw or ASae) having an top end (uppermost surface of items ASae or ASaw) that is higher than the top surface of chip/die (item 120) and physically contacts the lateral surface of the chip/die (item 120) as well,
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the coating of Lee for the purpose of protection.
In regards to claim 2, Muramatsu (Figs. 29, 30 and associated text) as modified by SUEHIRO (Figs. 1, 5, 6, 10 and associated text and equivalent items) and Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: the coating material (item 24, SUEHIRO, item 108, Lee) covers the top face, the lateral face, and a corner portion between the top face and the lateral face, of the semiconductor chip (item 30, Muramatsu, item 21, SUEHIRO) mounted in the recess (shown but not labeled, Muramatsu and SUEHIRO) of the conductive sintered member (items 20, 25, Muramatsu, item 22, SUEHRO).
In regards to claim 3, Muramatsu (Figs. 29, 30 and associated text) as modified by SUEHIRO (Figs. 1, 5, 6, 10 and associated text and equivalent items) and Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: porosity of the conductive sintered member (items 20, 25, Muramatsu, item 22, SUEHIRO) between the recess (shown but not labeled, Muramatsu) and the conductive pattern layer (item 12, Muramatsu, items 3, 43, 43a, 41, 41 plus 43, 41 plus 43a, 41 plus 43 plus 3 or 41 plus 43a plus 3, SUEHIRO) is lower than porosity of the frame (items 25t, 22, Muramatsu, item 22, SUEHIRO) in a cross-sectional view. Examiner notes that the sintered body of Muramatsu share the same materials and heating temperature range of the Applicant and would thus share the same characteristics.
In regards to claim 14, Muramatsu (Figs. 29, 30 and associated text) as modified by SUEHIRO (Figs. 1, 5, 6, 10 and associated text and equivalent items) and Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: the frame (items 25t, 25s, 22, 21, Muramatsu, item 22, SUEHIRO) and the semiconductor chip (item 30, Muramatsu, item 21, SUEHIRO) form a filling space (shown but not labeled, Muramatsu and SUEHRIO) that is a space surrounded by the frame (items 25t, 25s, 22, 21, Muramatsu, item 22, SUEHIRO) and, in a thickness direction of the semiconductor chip (item 30, Muramatsu, item 21, SUEHIRO), between the top end of the frame (items 25t, 25s, 22, 21, Muramatsu, item 22, SUEHIRO) and the top face of the semiconductor chip (item 30, Muramatsu, item 21, SUEHIRO); and the coating material (item 24, SUEHIRO) fully fills the filling space (shown but not labeled, Muramatsu and SUEHRIO).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shiraki (JP 2020024998 A, Fig. 6, item 13, conductive sintered body, item 14, chip, item 33, coating, item 30, conductive pattern layer) could have been used in place of SUEHIRO.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 July 20, 2026
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