DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3 have been considered but are moot on ground of new rejection and interpretation of the current prior art of record.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. (Muramatsu) (JP 2017220490A) view of Lee et al. (Lee) (US 2017/0005075 A1).
In regards to claim 1, Muramatsu (Figs. 29, 30 and associated text) discloses a semiconductor device (Figs. 29, 30), comprising: an insulated circuit board (item 10) including a conductive pattern layer (item 12); a sintered member (items 20, 25) disposed on the conductive pattern layer, the sinter member (items 20, 25) having a frame (items 25t, 25s, 22, 21) formed on a surface thereof opposite to the conductive pattern layer (item 12), to thereby form a recess (shown but not labeled) on the surface, the frame (items 25t, 22) shaping an outer edge of the recess (shown but not labeled); a semiconductor chip (item 30) having a top face (where item 33 resides), a bottom face (where item 32 resides) opposite to the top face (where item 33 resides), and a lateral face (lateral face of item 30 on the left and right), the semiconductor chip (item 30) being mounted in the recess (shown but not labeled) with the bottom face (where item 32 resides) opposing the recess (shown but not labeled), the bottom face (where item 32 resides) being located closer to the conductive pattern layer (item 12) than a top end (uppermost surface of items 25t and 22) of the frame (items 25, 22), but does not specifically disclose the top face being located closer to the conductive pattern layer than a top end of the frame; and a coating material covering the semiconductor chip mounted in the recess.
Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses a bonding member (item 140, AS, ASa plus ASaw, Asa plus ASae) that has portion (items ASaw or ASae) having an top end (uppermost surface of items ASae or ASaw) that is higher than the top surface of chip/die (item 120) and physically contacts the lateral surface of the chip/die (item 120); and a coating material (item 108) covering a semiconductor chip (item 120) in a recess (shown but not labeled, which is formed by compressing first NCF 140).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Lee for the purpose of protection and a mechanical bond since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Muramatsu (Figs. 29, 30 and associated text) as modified by Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses the top face (where item 33 resides, Muramatsu) being located closer to the conductive pattern layer (item 12, Muramatsu) than a top end (uppermost surface of items 25t and 22, Muramatsu, uppermost surface of items Asaw or Asae, Lee, Fig. 7A) of the frame (items 25, 20, Muramatsu, items 140, AS, ASa plus ASaw, Asa plus ASae, Lee, Fig. 7A).
In regards to claim 2, Muramatsu (Figs. 29, 30 and associated text) as modified by Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: the coating material (item 108, Lee) covers the top face, the lateral face, and a corner portion between the top face and the lateral face, of the semiconductor chip (item 30, Muramatsu) mounted in the recess (shown but not labeled, Muramatsu) of the sintered member (items 20, 25).
In regards to claim 3, Muramatsu (Figs. 29, 30 and associated text) as modified by Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: porosity of the sintered member (items 20, 25) between the recess (shown but not labeled, Muramatsu) and the conductive pattern layer (item 12) is lower than porosity of the frame (items 25t, 22) in a cross-sectional view. Examiner notes that the sintered body of Muramatsu share the same materials and heating temperature range of the Applicant and would thus share the same characteristics.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. (Muramatsu) (JP 2017220490A) as evidence by or in view of Koike et al. (Koike) (US 2021/0066234 A1) and/or Hwang et al. (Hwang) (US 2021/0151410 A1) view of Lee et al. (Lee) (US 2017/0005075 A1).
In regards to claim 1, Muramatsu (Figs. 29, 30 and associated text) discloses a semiconductor device (Figs. 29, 30), comprising: an insulated circuit board (item 10) including a conductive pattern layer (item 12); a sintered member (items 20, 25) disposed on the conductive pattern layer, the sinter member (items 20, 25) having a frame (items 25t, 25s, 22, 21) formed on a surface thereof opposite to the conductive pattern layer (item 12), to thereby form a recess (shown but not labeled) on the surface, the frame (items 25t, 22) shaping an outer edge of the recess (shown but not labeled); a semiconductor chip (item 30) having a top face (where item 33 resides), a bottom face (where item 32 resides) opposite to the top face (where item 33 resides), and a lateral face (lateral face of item 30 on the left and right), the semiconductor chip (item 30) being mounted in the recess (shown but not labeled) with the bottom face (where item 32 resides) opposing the recess (shown but not labeled), the bottom face (where item 32 resides) being located closer to the conductive pattern layer (item 12) than a top end (uppermost surface of items 25t and 22) of the frame (items 25, 22), but does not specifically disclose the top face being located closer to the conductive pattern layer than a top end of the frame.
As evidenced by Koike (Fig. 1A, 1B and associated text) teaches sinter/bonding member (item 30, paragraph 19) having a frame (items 32, 34), the frame (items 32, 34) shaping an outer edge of recess (shown but not labeled) can have a second portion (item 34) that is higher or lower than the first portion (item 32, paragraphs 23-25) as long as the angle q satisfies the condition of 80 degrees or less. Examiner notes Koike does not disclose any height restrictions, therefore even though it might not be shown in the figures, the height of the top end (uppermost surface of item 34) of the second portion (item 34) can be higher than the top surface of the semiconductor chip/die (item 20) if so desired.
As evidenced by Hwang (Figs. 12-14 and associated text), a bonding member (items 540, 540a or 640) that has portion (portion surrounding lateral surfaces of the chip/die 120) having an top end (uppermost surface of items 540, 540a or 640) that is even, lower than or higher than the top surface of chip/die (item 120).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate teachings of Koike or Hwang for the purpose mechanical and/or electrical bond, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Muramatsu as evidenced/modified by Koike or Hwang Muramatsu discloses the top face (where item 33 resides) being located closer to the conductive pattern layer (item 12) than a top end (uppermost surface of items 25t and 22, Muramatsu, uppermost surface of item 34, Koike, uppermost surface of items 540, 540a or 640, Hwang) of the frame (items 25, 22, Muramatsu, items 32, 34, Koike and Hwang).
Muramatsu as evidenced/modified by Koike or Hwang does not specifically disclose a coating material covering the semiconductor chip mounted in the recess.
Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses a bonding member (item 140, AS, ASa plus ASaw, Asa plus ASae) that has portion (items ASaw or ASae) having an top end (uppermost surface of items ASae or ASaw) that is higher than the top surface of chip/die (item 120) and physically contacts the lateral surface of the chip/die (item 120) as well, and coating material (item 108) covering a semiconductor chip (item 120) in a recess (shown but not labeled, which is formed by compressing first NCF 140).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the coating of Lee for the purpose of protection.
In regards to claim 2, Muramatsu (Figs. 29, 30 and associated text) as modified by Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: the coating material (item 108, Lee) covers the top face, the lateral face, and a corner portion between the top face and the lateral face, of the semiconductor chip (item 30, Muramatsu) mounted in the recess (shown but not labeled, Muramatsu) of the sintered member (items 20, 25).
In regards to claim 3, Muramatsu (Figs. 29, 30 and associated text) as modified by Lee (Figs. 1A-1D, 7A, 7B and associated text) discloses wherein: porosity of the sintered member (items 20, 25) between the recess (shown but not labeled, Muramatsu) and the conductive pattern layer (item 12) is lower than porosity of the frame (items 25t, 22) in a cross-sectional view. Examiner notes that the sintered body of Muramatsu share the same materials and heating temperature range of the Applicant and would thus share the same characteristics.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 November 19, 2025