DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US Publication No. 2021/0126113) in view of Ko et al (US Publication No. 2022/0367286).
Regarding claim 1, Lin discloses an integrated circuit structure Fig 1, comprising: a vertical stack of horizontal nanowires Fig 7A-7B, 701 over a first sub-fin Fig 7A-7B, 105; a gate structure Fig 8A-8B, 107 over the vertical stack of horizontal nanowires and on the first sub-fin Fig 8A-8B; a dielectric structure Fig 13A-13B, 111 laterally spaced apart from the gate structure Fig 13A-13B, 107, wherein the dielectric structure Fig 13A-13B, 111 is not over a channel structure Fig 13A-13B, 701 but is on a second sub-fin Fig 13A-13B, 105; and a gate cut Fig 13A-13B, 109 ¶0092 between the gate structure Fig 13A-13B, 107 and the dielectric structure Fig 13A-13B, 111. Lin discloses all the limitations but silent on the arrangement of the gate cut relative to the dielectric structure. Whereas Ko discloses the gate cut Fig 13, 58/60/70/72 or Fig 23, 58/70/72 having a bottommost surface below a bottommost surface of the dielectric structure Fig 7B, 50 or Fig 23, 50A/50B. Lin and Ko are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lin and incorporate the arrangement of the gate cut to improve device isolation.
Regarding claim 2, Lin discloses a dielectric gate cut plug in the gate cut¶0092.
Regarding claim 3, Lin discloses a second gate structure over a second vertical stack of horizontal nanowires and on a third sub-fin Fig 13A-13B, the second gate structure laterally spaced apart from the dielectric structure; a second gate cut between the second gate structure and the dielectric structure Fig 13A-13B; and a second dielectric gate cut plug in the second gate cut Fig 13A-13B.
Regarding claim 4, Lin discloses wherein the second sub-fin has a top surface below a top surface of the first sub-fin Fig 13B.
Regarding claim 5, Lin discloses an epitaxial source or drain structure at an end of the vertical stack of horizontal nanowires ¶0108.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US Publication No. 2021/0126113) in view of Guler et al (US Publication No. 20220093592) and Ko et al (US Publication No. 2022/0367286).
Regarding claim 6, Lin discloses an integrated circuit structure Fig 1, comprising: a vertical stack of horizontal nanowires Fig 7A-7B, 701 over a first sub-fin Fig 7A-7B, 105; a gate structure Fig 8A-8B, 107 over the vertical stack of horizontal nanowires and on the first sub-fin Fig 8A-8B; a dielectric structure Fig 13A-13B, 111 laterally spaced apart from the gate structure Fig 13A-13B, 107, wherein the dielectric structure Fig 13A-13B, 111 is not over a channel structure Fig 13A-13B, 701 but is on a second sub-fin Fig 13A-13B, 105; and a gate cut Fig 13A-13B, 109 ¶0092 between the gate structure Fig 13A-13B, 107 and the dielectric structure Fig 13A-13B, 111. Lin discloses all the limitation but silent on the type of channel. Whereas Guler discloses an integrated circuit structure, comprising: a fin over a first sub-fin Fig 6; a gate structure over the fin Fig 8A-8C. Lin and Guler are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lin and incorporate the type of channel region of Guler as an alternative channel known in the art. Lin and Guler discloses all the limitations but silent on the arrangement of the gate cut relative to the dielectric structure. Whereas Ko discloses the gate cut Fig 13, 58/60/70/72 or Fig 23, 58/70/72 having a bottommost surface below a bottommost surface of the dielectric structure Fig 7B, 50 or Fig 23, 50A/50B. Lin and Ko are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lin and incorporate the arrangement of the gate cut to improve device isolation.
Regarding claim 7, Lin discloses a dielectric gate cut plug in the gate cut Fig 13A-13B.
Regarding claim 8, Lin in view of Guler discloses a second gate structure over a second vertical stack of horizontal nanowires and on a third sub-fin Fig 13A-13B, the second gate structure laterally spaced apart from the dielectric structure; a second gate cut between the second gate structure and the dielectric structure Fig 13A-13B; and a second dielectric gate cut plug in the second gate cut Fig 13A-13B.
Regarding claim 9, Lin discloses wherein the second sub-fin has a top surface below a top surface of the first sub-fin Fig 13B.
Regarding claim 10, Lin discloses an epitaxial source or drain structure at an end of the vertical stack of horizontal nanowires ¶0108.
Regarding claim 11, Lin discloses an integrated circuit structure Fig 1, comprising: a vertical stack of horizontal nanowires Fig 7A-7B, 701 over a first sub-fin Fig 7A-7B, 105; a gate structure Fig 8A-8B, 107 over the vertical stack of horizontal nanowires and on the first sub-fin Fig 8A-8B; a dielectric structure Fig 13A-13B, 111 laterally spaced apart from the gate structure Fig 13A-13B, 107, wherein the dielectric structure Fig 13A-13B, 111 is not over a channel structure Fig 13A-13B, 701 but is on a second sub-fin Fig 13A-13B, 105; and a gate cut Fig 13A-13B, 109 ¶0092 between the gate structure Fig 13A-13B, 107 and the dielectric structure Fig 13A-13B, 111. Lin discloses all the limitations but silent on applying the integrated circuit structure to a computing device. Whereas Guler discloses a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure Fig 9. Lin and Guler are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lin and incorporate the teachings of Guler to provide a product that optimize performance ¶0002. Lin and Guler discloses all the limitations but silent on the arrangement of the gate cut relative to the dielectric structure. Whereas Ko discloses the gate cut Fig 13, 58/60/70/72 or Fig 23, 58/70/72 having a bottommost surface below a bottommost surface of the dielectric structure Fig 7B, 50 or Fig 23, 50A/50B. Lin and Ko are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lin and incorporate the arrangement of the gate cut to improve device isolation.
Regarding claim 12, Guler discloses a memory coupled to the board Fig 9.
Regarding claim 13, Guler discloses a communication chip coupled to the board Fig 9.
Regarding claim 14, Guler discloses wherein the component is a packaged integrated circuit die Fig 9.
Regarding claim 15, Guler discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor Fig 9.
Regarding claim 16, Lin discloses an integrated circuit structure Fig 1, comprising: a vertical stack of horizontal nanowires Fig 7A-7B, 701 over a first sub-fin Fig 7A-7B, 105; a gate structure Fig 8A-8B, 107 over the vertical stack of horizontal nanowires and on the first sub-fin Fig 8A-8B; a dielectric structure Fig 13A-13B, 111 laterally spaced apart from the gate structure Fig 13A-13B, 107, wherein the dielectric structure Fig 13A-13B, 111 is not over a channel structure Fig 13A-13B, 701 but is on a second sub-fin Fig 13A-13B, 105; and a gate cut Fig 13A-13B, 109 ¶0092 between the gate structure Fig 13A-13B, 107 and the dielectric structure Fig 13A-13B, 111. Lin discloses all the limitation but silent on the type of channel and also Lin is silent on applying the integrated circuit structure to a computing device. Whereas Guler discloses an integrated circuit structure, comprising: a fin over a first sub-fin Fig 6; a gate structure over the fin Fig 8A-8C. Guler also discloses a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure Fig 9. Lin and Guler are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lin and incorporate the type of channel region of Guler as an alternative channel known in the art. Also, the teachings of Guler to provide a product that optimize performance ¶0002. Lin and Guler discloses all the limitations but silent on the arrangement of the gate cut relative to the dielectric structure. Whereas Ko discloses the gate cut Fig 13, 58/60/70/72 or Fig 23, 58/70/72 having a bottommost surface below a bottommost surface of the dielectric structure Fig 7B, 50 or Fig 23, 50A/50B. Lin and Ko are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lin and incorporate the arrangement of the gate cut to improve device isolation.
Regarding claim 17, Guler discloses a memory coupled to the board Fig 9.
Regarding claim 18, Guler discloses a communication chip coupled to the board Fig 9.
Regarding claim 19, Guler discloses wherein the component is a packaged integrated circuit die Fig 9.
Regarding claim 20, Guler discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor Fig 9.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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