DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-11 in the reply filed on 10/29/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishida(USPGPUB DOCUMENT: 2019/0189529, hereinafter Nishida) in view of Nakamura (USPGPUB DOCUMENT: 2019/0287887, hereinafter Nakamura).
Re claim 1 Nishida discloses a semiconductor device manufacturing method, comprising: a preparing process for preparing a conductive plate(3a)[0117], a semiconductor chip(semiconductor chip)[0041] arranged over the conductive plate(3a)[0117], and a connection terminal(7a/7b)[0048] including a bonding portion(5a/8) arranged over the semiconductor chip(semiconductor chip)[0041] ; a first jig arrangement process for arranging a first guide jig, through which a first guide hole(5a1) pierces, over the conductive plate(3a)[0117], such that the first guide hole(5a1) corresponds to the bonding portion(5a/8) in a plan view of the semiconductor device; and a first pressing process[0054] for inserting a pillar-shaped pressing jig(7a), which includes a pressing portion[0059,0060] at a lower end portion thereof, into the first guide hole(5a1), and pressing the bonding portion(5a/8) of the connection terminal(7a/7b)[0048] to a side of the conductive plate(3a)[0117] with the pressing portion[0059,0060].
Nishida does not discloses a semiconductor chip(semiconductor chip)[0041] arranged over the conductive plate(3a)[0117] with a first bonding material therebetween, and a connection terminal(7a/7b)[0048] including a bonding portion(5a/8) arranged over the semiconductor chip(semiconductor chip)[0041] with a second bonding material therebetween;
Nakamura discloses a bonding material (7)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Nakamura to the teachings of Nishida in order to offer increased bond strength between an insulated circuit board, external terminals, and a printed circuit board and also offer excellent manufacturability [0017, Nakamura]. In doing so, a semiconductor chip(semiconductor chip)[0041] arranged over the conductive plate(3a)[0117] with a first bonding material (7 of Nakamura) therebetween, and a connection terminal(7a/7b)[0048] including a bonding portion(5a/8) arranged over the semiconductor chip(semiconductor chip)[0041] with a second bonding material (7 of Nakamura) therebetween;
Re claim 2 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 1, wherein the first pressing process[0054] further includes performing heating while pressing the bonding portion(5a/8) of the connection terminal(7a/7b)[0048] with the pressing portion[0059,0060] of the pressing jig(7a).
Re claim 3 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 1, wherein the pressing jig(7a) further includes, at an upper end portion thereof, a locking portion lockable by the first guide jig(7a).
Re claim 4 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 1, wherein the preparing process further includes providing an insulated circuit board that has: an insulating plate, the conductive plate(3a)[0117], which is formed on a front surface of the insulating plate, and a metal plate formed on a back surface of the insulating plate.
Re claim 5 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 4, wherein the preparing process further includes preparing a radiation plate and the insulated circuit board, and the semiconductor device manufacturing method further includes, after the first pressing process[0054], a second pressing process[0054] for arranging the insulated circuit board, to which the semiconductor chip(semiconductor chip)[0041] and the bonding portion(5a/8) of the connection terminal(7a/7b)[0048] are bonded in order, over the radiation plate with a third bonding material therebetween, and pressing the bonding portion(5a/8) of the connection terminal(7a/7b)[0048] with the pressing jig(7a).
Re claim 6 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 5, wherein the second pressing process[0054] further includes performing heating while pressing the bonding portion(5a/8) of the connection terminal(7a/7b)[0048] with the pressing portion[0059,0060] of the pressing jig(7a).
Re claim 7 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 5, wherein the second pressing process[0054] further includes arranging a spacer jig(7a) having an opening portion, such that the opening portion corresponds to the semiconductor chip(semiconductor chip)[0041], and the semiconductor chip(semiconductor chip)[0041] and the bonding portion(5a/8) of the connection terminal(7a/7b)[0048] are in the opening portion in the plan view, and arranging the first guide jig(7a) on the spacer jig.
Re claim 8 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 7, wherein a height of the opening portion of the spacer jig is greater than a sum of a height of the semiconductor chip(semiconductor chip)[0041] and a height of the bonding portion(5a/8) of the connection terminal(7a/7b)[0048] arranged over the semiconductor chip(semiconductor chip)[0041].
Re claim 9 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 7, wherein arranging the spacer jig(7a) includes forming a guide portion extending toward the bonding portion(5a/8) on an inside of the opening portion of the spacer jig.
Re claim 10 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 1, wherein the first pressing process[0054] further includes forming a semiconductor unit by bonding the semiconductor chip(semiconductor chip)[0041] to the conductive plate(3a)[0117] with the first bonding material, and by bonding the bonding portion(5a/8) of the connection terminal(7a/7b)[0048] to the semiconductor chip(semiconductor chip)[0041] with the second bonding material.
Re claim 11 Nishida and Nakamura disclose the semiconductor device manufacturing method according to claim 1, wherein: the pressing portion[0059,0060] of the pressing jig(7a) has a flat surface, with a concave housing portion formed in the flat surface for the bonding portion(5a/8) of the connection terminal(7a/7b)[0048] to be housed therein.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812