DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 1/14/26 have been fully considered but they are not persuasive. Applicant has amended the independent claims to include the limitation “wherein the semiconductor channel varies in vertical thickness along a direction orthogonal to and in a same horizontal plane as the source drain direction” and argues that Lee does not teach such details because fig. 9 discloses a same vertical thickness in the y direction which is orthogonal to the source to drain direction (x direction). This is not persuasive because the z direction is also orthogonal to the source to drain direction (x direction) as mentioned in the rejection below. To summarize, the source to drain direction is the x direction (fig. 2), the z direction is orthogonal to the x direction (fig. 2), the semiconductor channel 120 (figs. 2-3) clearly varies in vertical thickness and the limitation “in a same horizontal plane as the source drain direction” lacks reference.
Applicant is advised to amend the independent claims 1, 11, 17 and 23 to include language to explicitly disclose Applicant’s invention. Examiner suggests the following claim language:
a substrate;
“wherein the semiconductor channel varies in vertical thickness along a direction that is perpendicular to the source to drain direction and is parallel to the substrate”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-13, 15-17 and 20-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2017/0345945).
Regarding claim 1, Lee discloses a transistor, comprising:
a source (150, fig. 2 and paragraph 0042);
a drain (150, fig. 2 and paragraph 0042);
a pair of spacers between the source and the drain (140, fig. 2 and paragraphs 0057-0060);
a semiconductor channel (120, figs. 2-3 and paragraph 0053) between the source and the drain along a source to drain direction (x direction, fig. 3), where the semiconductor channel passes through the pair of spacers (fig. 2 and paragraph 0058), and wherein the semiconductor channel has a first vertical thickness within the pair of spacers (t2, fig. 3 and paragraphs 0070, 0092) and a second vertical thickness between the pair of spacers (t1, fig. 3 and paragraphs 0070, 0092), wherein the second vertical thickness is less than the first vertical thickness (fig. 3 and paragraphs 0070, 0092), and wherein the semiconductor channel varies in vertical thickness along a direction orthogonal to and in the same horizontal plane as the source to drain direction (z direction, t1, t2, figs. 2-3); and
a gate stack over the semiconductor channel between the pair of spacers (130, fig. 2 and paragraph 0055).
Regarding claim 2, Lee further discloses wherein the semiconductor channel is a nanoribbon, a nanowire, or a nanosheet (120, figs. 2-3 and paragraph 0053).
Regarding claim 4, Lee further discloses wherein the semiconductor channel has an oval shaped cross- section when viewed in a plane parallel to the gate stack (paragraph 0052).
Regarding claim 5, Lee further discloses wherein the gate stack comprises a gate dielectric around the semiconductor channel, and a workfunction metal over the gate dielectric (fig. 2 and paragraph 0055).
Regarding claim 6, Lee further discloses a plurality of semiconductor channels in a vertical stack between the source and the drain (figs. 16, 19).
Regarding claim 7, Lee further discloses wherein the plurality of semiconductor channels comprises at least four semiconductor channels (fig. 19 and paragraph 0136).
Regarding claim 8, Lee further discloses wherein the semiconductor channel comprises silicon (paragraph 0053).
Regarding claim 9, Lee further discloses wherein the semiconductor channel is provided above a semiconductor fin (paragraph 0051).
Regarding claim 10, Lee further discloses wherein a width of the semiconductor channel is substantially equal to a width of the semiconductor fin (fig. 4).
Regarding claim 11, Lee discloses a semiconductor structure, comprising:
a first transistor with a first semiconductor channel (120, fig. 19 and paragraphs 0122-0136);
a second transistor with a second semiconductor channel (125, fig. 19 and paragraphs 0122-0136); and
a gate stack across the first semiconductor channel and the second semiconductor channel (130, fig. 19 and paragraphs 0122-0136), wherein the gate stack comprises:
a first workfunction metal (paragraph 0055) over the first semiconductor channel; and
a second workfunction metal (paragraph 0055) over the second semiconductor channel, wherein the first semiconductor channel and the second semiconductor channel comprise a dumbbell shaped cross-section when viewed in a plane orthogonal to the gate stack (fig. 19 and paragraph 0213), and wherein each of the first semiconductor channel and the second semiconductor channel varies in vertical thickness along a direction orthogonal to and in a same horizontal plane as a source to drain direction (z direction is orthogonal to the x direction, fig. 19).
Regarding claim 12, Lee further discloses wherein the first semiconductor channel and the second semiconductor channel are nanoribbons, nanowires, or nanosheets (120, fig. 19 and paragraph 0053).
Regarding claim 13, Lee further discloses wherein the dumbbell shaped cross-section includes ends with a first vertical thickness and a center with a second vertical thickness that is smaller than the first vertical thickness (fig. 19).
Regarding claim 15, Lee further discloses wherein the ends of the first semiconductor channel and the second semiconductor channel pass through spacers, wherein the centers of the first semiconductor channel and the second semiconductor channel are between the spacers (fig. 19 paragraph 0058).
Regarding claim 16, Lee further discloses wherein the first semiconductor channel and the second semiconductor channel include oval shaped cross-sections when viewed in a plane parallel to the gate stack (paragraph 0052).
Regarding claim 17, Lee discloses a method of forming a semiconductor structure, comprising:
forming a transistor, comprising:
a source (150, fig. 2 and paragraph 0042);
a drain (150, fig. 2 and paragraph 0042);
a pair of spacers between the source and the drain (140, fig. 2 and paragraphs 0057-0060); and
a semiconductor channel (120, fig. 2 and paragraph 0053) between the source and the drain that passes through the pair of spacers (paragraph 0058) along a source to drain direction (x direction, fig. 2), wherein the semiconductor channel has a first vertical thickness; etching the semiconductor channel (paragraph 0104), wherein the etching results in the semiconductor channel having the first vertical thickness within the pair of spacers (t2, fig. 3) and a second vertical thickness between the pair of spacers (t1, fig. 3), wherein the second vertical thickness is smaller than the first vertical thickness (fig. 3 and paragraphs 0070, 0092), and wherein the semiconductor channel varies in vertical thickness along a direction orthogonal to and in a same horizontal plane as the source to drain direction (z direction, t1, t2, figs. 2-3); and
forming a gate stack over the semiconductor channel between the pair of spacers (130, fig. 2 and paragraph 0055).
Regarding claim 20, Lee further discloses wherein the semiconductor channel has an oval cross-section when viewed in a plane parallel to the gate stack (paragraph 0052).
Regarding claim 21, Lee further discloses wherein the gate stack comprises a gate dielectric and a workfunction metal (fig. 2 and paragraph 0055).
Regarding claim 22, Lee further discloses wherein the semiconductor channel is a nanoribbon, a nanowire, or a nanosheet (120, figs. 2-3 and paragraph 0053).
Regarding claim 23, Lee discloses a computing system, comprising:
a board; a component coupled to the board (fig. 63 and paragraphs 0256-0259), wherein the component comprises an integrated circuit structure that comprises: a transistor with a semiconductor channel between a source and a drain along a source to drain direction (x direction, fig. 2), wherein the semiconductor channel passes through a pair of spacers, and wherein the semiconductor channel has a first vertical thickness within the pair of spacers and a second vertical thickness between the spacers, wherein the second vertical thickness is less than the first vertical thickness (fig. 2 and paragraphs 0042-0060) and wherein the semiconductor channel varies in vertical thickness along a direction orthogonal to the source to drain direction (z direction, t1, t2, figs. 2-3).
Regarding claim 24, Lee further discloses comprising: a memory coupled to the board (fig. 63 and paragraphs 0256-0259).
Regarding claim 25, Lee further discloses further comprising: a communication chip coupled to the board (fig. 63 and paragraphs 0256-0259).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 14 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2017/0345945).
Regarding claims 3 and 14, Lee discloses the transistor and semiconductor structure of claims 1 and 13 as mentioned above. Lee does not explicitly disclose wherein the first vertical thickness is approximately 1nm or more than the second vertical thickness.
However, Lee explicitly discloses nanowires and as such, it is understood that the variations of 1 nm or more would be deemed obvious to one of ordinary skill in the art at the time of filing given Lee’s disclosure.
Regarding claims 18-19, Lee discloses the method of claim 17 as mentioned above. Lee does not explicitly disclose wherein the etching is an isotropic etching process or wherein the etching uses a DEA and/or a DHF etching chemistry. However, such practices were well known in the art and commonly practiced at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 4/30/26
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