DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-5, 9, 13-19, 27-32 pending. Claim 29 withdrawn. Claims 6-8, 10-12, 20-26 canceled.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 23, 2026 has been entered.
Election/Restrictions
Claim 29 recites the limitation “wherein: the second metal layer has a multi-layered structure including a conductive adhesion layer facing the silicon-germanium semiconductor layer, and the bottom surface of the first contact plug does not contact the conductive adhesion layer” in the claim language.
Claim 29 reads upon non-elected species V: FIG. 9, which requires ([0092]) As shown in FIG. 9, the cell contact plug MC2 may have a bottom surface in contact with the second metal layer ML2 (e.g., the second sub-metal layer 22). The cell contact plug MC2 may have a lower sidewall in contact with the silicon layer SL2.
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Claim 29 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected elected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 28, 2025.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “top electrode on the dielectric layer and between the plurality of bottom electrodes, wherein the top electrode includes a first metal layer, a silicon-germanium semiconductor layer, a second metal layer, and a silicon semiconductor layer that are sequentially stacked” in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Therefore, the “top electrode on the dielectric layer and between the plurality of bottom electrodes, wherein the top electrode includes a first metal layer, a silicon-germanium semiconductor layer, a conductive adhesion layer, a second metal layer, and a silicon semiconductor layer that are sequentially stacked” in claim 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 30, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 28 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 28. Claim 28 recites the limitation “wherein the second metal layer does not extend between neighboring ones of the plurality of bottom electrodes” in the claim language.
Claim 28 depends upon claim 1. Claim 1 requires the limitation a top electrode on the dielectric layer and between the plurality of bottom electrodes, wherein the top electrode includes a first metal layer, a silicon-germanium semiconductor layer, a second metal layer, and a silicon semiconductor layer that are sequentially stacked.
Applicant appears to be claiming that the second metal electrode is between the plurality of bottom electrodes in claim 1 and then not between the plurality of bottom electrodes in dependent claim 28.
Claim 28 and claim 1 appear to claim two mutually exclusive limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 9, 13-19, 28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. 2018/0166529), and further in view of Nam et al (U.S. 2006/0186452) with Heo et al (U.S. 2021/0296321) as support evidence and Dellasega et al (High energy pulsed laser deposition of ohmic tungsten contacts on silicon at room temperature as support evidence, 2018).
Regarding claim 1. Park et al discloses a semiconductor memory device (FIG. 6), comprising:
a semiconductor substrate (FIG. 6, item 1) that includes a cell array region (FIG. 6, item A) and a peripheral region (FIG. 6, item B);
a plurality of bottom electrodes (FIG. 6, item BE) on the semiconductor substrate (FIG. 6, item 1) on the cell array region (FIG. 6, item A);
a dielectric layer (FIG. 6, item 30) that conformally covers sidewalls and top surfaces of the bottom electrodes (FIG. 6, item BE); and
a top electrode (FIG. 6, item UE, 53 and 56) on the dielectric layer (FIG. 6, item 30), wherein the top electrode (FIG. 6, item UE) includes a first metal layer (FIG. 6, item 32), a silicon-germanium semiconductor layer (FIG. 6, item 34; [0017]), a second metal layer (FIG. 6, item 53) sequentially stacked.
Park et al fails to explicitly disclose top electrode between the between the plurality of bottom electrode, a silicon-germanium semiconductor layer, a second metal layer, and a silicon semiconductor layer that are sequentially stacked, and wherein an amount of boron in the silicon-germanium semiconductor layer is greater than an amount of boron in the silicon semiconductor layer.
However, Nam et al teaches
wherein the a top electrode between (FIG. 8, item 190) the between the plurality of bottom electrodes (FIG. 8, item 140a) includes a first metal layer (FIG. 8, item 160), a silicon-germanium semiconductor layer (FIG. 8, item 170; Claim 19), a second metal layer (FIG. 8, item 175), and a silicon semiconductor layer (FIG. 8, item 180; [0037]) that are sequentially stacked ([Abstract]), and wherein an amount of boron in the silicon-germanium semiconductor layer (Claim 19, B-doped silicon germanium) is greater than an amount of boron in the silicon semiconductor layer (FIG. 2, item 180; [0037] i.e. The third conductive layer 180 is for example, WSix).
Heo et al discloses as evidence [0035] that tungsten silicide is a metal-semiconductor compound.
Dellasega et al disclose as evidence [56] the WSi system may display a barrier reduction also due to the fact that the bandgap of crystalline W silicide is about 0.3–0.4 eV
Since Park et al and Nam et al teach capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Park et al with the teachings of top electrode between the between the plurality of bottom electrode, a silicon-germanium semiconductor layer, a second metal layer, and a silicon semiconductor layer that are sequentially stacked, and wherein an amount of boron in the silicon-germanium semiconductor layer is greater than an amount of boron in the silicon semiconductor layer as disclosed by Nam et al. The use of the third conductive layer is formed of a material having lower resistance than that of the doped polysilicon germanium of the second conductive layer for example, WSix in Nam et al provides for the third conductive layer comprises a material having a lower resistance than that of the second conductive layer (Nam et al, [ABSTRACT]).
Regarding claim 2. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 1 above.
Park et al further discloses wherein a surface roughness at a top surface of the silicon semiconductor layer is less than a surface roughness at a lateral surface of the silicon semiconductor layer ([Abstract], i.e. A surface roughness of a top surface of the upper electrode may be less than a surface roughness of a side surface of the upper electrode).
Regarding claim 3. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 1 above.
Nam et al further discloses wherein the second metal layer (FIG. 8, item 175) includes a conductive adhesion layer ([0040]) facing the silicon-germanium semiconductor layer (FIG. 8, item 170).
Regarding claim 4. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 3 above.
Nam et al further discloses wherein the conductive adhesion layer is formed of titanium ([0040], i.e. The barrier layer 175 is formed of TiN or Ti/TiN).
Regarding claim 5. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 1 above.
Park et al further discloses further comprising: an interlayer dielectric layer (FIG. 2, item 48) that covers the top electrode (FIG. 2, item UE); and a first contact plug (FIG. 2, item UE) that penetrates the interlayer dielectric layer (FIG. 2, item 48) to contact the top electrode (FIG. 2, item UE), wherein a bottom surface of the first contact plug (FIG. 2, item 54) is in contact with the second metal layer (FIG. 2, item 53).
Nam et al discloses the second metal layer (FIG. 8, item 175), and wherein the silicon semiconductor layer (FIG. 8, item 180; [0037]) does not include boron (FIG. 8, item 180; [0037]).
Regarding claim 9. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 1 above.
Park et al further discloses wherein lower sidewalls of the first metal layer (FIG. 4, item 32), the silicon-germanium semiconductor layer (FIG. 4, item 34) are vertically aligned ([0035]) with each other adjacent to a boundary (Claim 19) between the cell array region (FIG. 4, item A) and the peripheral region (FIG. 4, item B).
Nam et al further discloses the first metal layer (FIG. 8, item 160), the silicon-germanium semiconductor layer (FIG. 8, item 170; Claim 19), the second metal layer (FIG. 8, item 175), and the silicon semiconductor layer (FIG. 8, item 180; [0037])
Regarding claim 13. Park et al discloses a semiconductor memory device (FIG. 6), comprising:
a semiconductor substrate (FIG. 6, item 1) that includes a cell array region (FIG. 6, item A) and a peripheral region (FIG. 6, item B);
a plurality of bottom electrodes (FIG. 6, item BE) on the semiconductor substrate (FIG. 6, item 1) on the cell array region (FIG. 6, item A);
a dielectric layer (FIG. 6, item 30) that conformally covers sidewalls and top surfaces of the plurality bottom electrodes (FIG. 6, item BE); and
a top electrode (FIG. 6, item UE) on the dielectric layer (FIG. 6, item 30) and between the bottom electrodes (FIG. 6, item BE),
wherein the top electrode (FIG. 6, item UE) includes a first metal layer (FIG. 6, item 32), a silicon-germanium semiconductor layer (FIG. 6, item 34; [0017]),
Park et al fails to explicitly disclose a top electrode between the plurality of bottom electrodes, a second metal layer, and a silicon semiconductor layer that are sequentially stacked.
However, Nam et al discloses a top electrode between (FIG. 8, item 190) the between the plurality of bottom electrodes (FIG. 8, item 140a)
wherein the top electrode (FIG. 8, item 190) includes a first metal layer (FIG. 8, item 160), a silicon-germanium semiconductor layer (FIG. 8, item 170; Claim 18), a second metal layer (FIG. 8, item 175), and a silicon semiconductor layer (FIG. 8, item 180; [0037], i.e. for example WSix) that are sequentially stacked ([Abstract])
Heo et al discloses as evidence [0035] that tungsten silicide is a metal-semiconductor compound.
Dellasega et al disclose as evidence [56] the WSi system may display a barrier reduction also due to the fact that the bandgap of crystalline W silicide is about 0.3–0.4 eV
Since Park et al and Nam et al teach capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Park et al with the teachings of a second metal layer, and a silicon semiconductor layer that are sequentially stacked as disclosed by Nam et al. The use of The third conductive layer is formed of a material having lower resistance than that of the doped polysilicon germanium of the second conductive layer for example, WSix in Nam et al provides for the third conductive layer comprises a material having a lower resistance than that of the second conductive layer (Nam et al, [ABSTRACT]).
Regarding claim 14. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 13 above.
Nam et al further discloses wherein an amount of boron in the silicon-germanium semiconductor layer (Claim 19, B-doped silicon germanium) is greater than an amount of boron in the silicon semiconductor layer (FIG. 2, item 180; [0037] i.e. The third conductive layer 180 is formed of a material having lower resistance than that of the doped polysilicon germanium of the second conductive layer 170. For example, WSix).
Regarding claim 15. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 13 above.
Park et al further discloses further comprising: an interlayer dielectric layer (FIG. 2, item 48) that covers the top electrode (FIG. 2, item UE); and a first contact plug (FIG. 2, item UE) that penetrates the interlayer dielectric layer (FIG. 2, item 48) to contact the top electrode (FIG. 2, item UE), wherein a bottom surface of the first contact plug (FIG. 2, item 54) is in contact with the second metal layer (FIG. 2, item 53).
Nam et al discloses the second metal layer (FIG. 8, item 175), and wherein the silicon semiconductor layer (FIG. 8, item 180; [0037]) does not include boron (FIG. 8, item 180; [0037]).
Regarding claim 16. Park et al discloses a semiconductor memory device (FIG. 1-2), comprising:
a semiconductor substrate (FIG. 1, item 1) that includes a cell array region (FIG. 1, item A) and a peripheral region (FIG. 1, item B);
a word line (FIG. 2, item WL) in the semiconductor substrate on the cell array region ([0014]);
a first impurity region in the semiconductor substrate on one side of the word line ([0014], i.e. A first impurity region 5 may be disposed in the semiconductor substrate 1 on a side of each of the word lines WL);
a second impurity region in the semiconductor substrate on another side of the word line ([0014], i.e. a second impurity region 7 may be disposed in the semiconductor substrate 1 on the other side of each of the wordlines WL);
a bit line (FIG. 2, item BL) disposed on the semiconductor substrate (FIG. 2, item 1) on the cell array region (FIG. 2, item A) and connected to the first impurity region (FIG. 2, item 7), the bit line (FIG. 1, item BL) crossing over the word line (FIG. 1, item WL);
a bottom electrode (FIG. 2, item BE) disposed on the semiconductor substrate (FIG. 2, item 1) on the cell array region (FIG. 2, item A) and connected to the second impurity region (FIG. 2, item 5);
a dielectric layer (FIG. 2, item 30) that conformally covers a sidewall and a top surface of the bottom electrode (FIG. 2, item BE); and
a top electrode (FIG. 2, item UE) on the dielectric layer (FIG. 2, item 30), wherein the top electrode (FIG. 2, item UE) includes a first metal layer (FIG. 2, item 32), a silicon-germanium semiconductor layer (FIG. 2, item 34),
wherein a surface roughness ([0018]) at a top surface of the silicon semiconductor layer ([0018]) is equal to or less than about 10 nm root mean square (RMS) ([0018]), and
wherein a surface roughness ([0018]) at a lateral surface of the silicon semiconductor layer ([0018]) is greater than about 10 nm root mean square (RMS) and equal to or less than about 1,000 nm root mean square (RMS) ([0018]).
Park et al fails to explicitly disclose a second metal layer, and a silicon semiconductor layer that are sequentially stacked.
However, Nam et al discloses
wherein the top electrode (FIG. 8, item 190) includes a first metal layer (FIG. 8, item 160), a silicon-germanium semiconductor layer (FIG. 8, item 170; Claim 18), a second metal layer (FIG. 8, item 175), and a silicon semiconductor layer (FIG. 8, item 180; [0037], i.e. for example WSix) that are sequentially stacked ([Abstract])
Heo et al discloses as evidence [0035] that tungsten silicide is a metal-semiconductor compound.
Dellasega et al disclose as evidence [56] the WSi system may display a barrier reduction also due to the fact that the bandgap of crystalline W silicide is about 0.3–0.4 eV
Since Park et al and Nam et al teach capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Park et al with the teachings of a second metal layer, and a silicon layer that are sequentially stacked as disclosed by Nam et al. The use of The third conductive layer is formed of a material having lower resistance than that of the doped polysilicon germanium of the second conductive layer for example, WSix in Nam et al provides for the third conductive layer comprises a material having a lower resistance than that of the second conductive layer (Nam et al, [ABSTRACT]).
Regarding claim 17. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 16 above.
Nam et al further discloses wherein an amount of boron in the silicon-germanium semiconductor layer (Claim 19, B-doped silicon germanium) is greater than an amount of boron in the silicon semiconductor layer (FIG. 2, item 180; [0037] i.e. The third conductive layer 180 is formed of a material having lower resistance than that of the doped polysilicon germanium of the second conductive layer 170. For example, WSix).
Regarding claim 18. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 16 above.
Park et al further discloses further comprising: an interlayer dielectric layer (FIG. 2, item 48) that covers the top electrode (FIG. 2, item UE); and a first contact plug (FIG. 2, item UE) that penetrates the interlayer dielectric layer (FIG. 2, item 48) to contact the top electrode (FIG. 2, item UE), wherein a bottom surface of the first contact plug (FIG. 2, item 54) is in contact with the second metal layer (FIG. 2, item 53).
Nam et al discloses the second metal layer (FIG. 8, item 175), and wherein the silicon semiconductor layer (FIG. 8, item 180; [0037]) does not include boron (FIG. 8, item 180; [0037]).
Regarding claim 19. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 16 above.
Nam et al further discloses wherein the top electrode further includes a conductive adhesion layer (FIG. 8, item 175; [0040], i.e. Ti of Ti/TiN) between the silicon-germanium semiconductor layer (FIG. 8, item 170; [0035]; Claim 19) and the second metal layer (FIG. 8, item 175, [0040], i.e. TiN of Ti/TiN).
"Products of identical chemical composition cannot have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. Id. (Applicant argued that the claimed composition was a pressure sensitive adhesive containing a tacky polymer while the product of the reference was hard and abrasion resistant. "The Board correctly found that the virtual identity of monomers and procedures sufficed to support a prima facie case of unpatentability of Spada’s polymer latexes for lack of novelty.") MPEP 2112.01 II.
Regarding claim 28. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 2 above.
Park et al further discloses wherein the second metal layer (FIG. 8, item 53) does not extend between (FIG. 8 shows item 53 does not extend between items 46) neighboring ones of the plurality of bottom electrodes (FIG. 8, item BE)
Regarding claim 30. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 2 above.
Park et al further discloses wherein: top (FIG. 6, item 44) and lateral (FIG. 6, item 46) surfaces of the silicon-germanium semiconductor layer (FIG. 6, item 34) have the same roughness as one another ([0018], i.e. the top surface 44 of the silicon germanium layer 34 may be flat to exhibit a surface roughness of about 10 nm RMS .. The side surface 46 of the silicon germanium layer 34 may exhibit a surface roughness between about 10 nm RMS (Root Mean Square),
Park et al fails to explicitly disclose top and lateral surfaces of the second metal layer have the same roughness as one another.
However, Park teaches a second metal (FIG. 6, item 53) made of titanium/titanium nitride layer ([0054]) and is conformally covers the surfaces of silicon germanium layer (FIG. 6, item 44).
Applicant discloses ([0052]) the second metal layer is a single-layered or multi-layered structure formed of at least one selected from titanium, titanium nitride and conformally coats the silicon germanium top and lateral surfaces of the second metal layer have the same roughness as one another.
Since Park et al disclose discloses the same process and materials as applicant, Park et al inherently discloses top and lateral surfaces of the second metal layer have the same roughness as one another.
"Products of identical chemical composition cannot have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. Id. (Applicant argued that the claimed composition was a pressure sensitive adhesive containing a tacky polymer while the product of the reference was hard and abrasion resistant. "The Board correctly found that the virtual identity of monomers and procedures sufficed to support a prima facie case of unpatentability of Spada’s polymer latexes for lack of novelty.") MPEP 2112.01 II
Claims 27, 31 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (U.S. 2018/0166529), and Nam et al (U.S. 2006/0186452) with Heo et al (U.S. 2021/0296321) as support evidence and Dellasega et al (High energy pulsed laser deposition of ohmic tungsten contacts on silicon at room temperature as support evidence, 2018) as applied to claims 1, 13 and 16 above respectively, and further in view of Tamura et al (U.S. 5,641,985)
Regarding claim 27. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 1 above.
Name et al discloses the silicon semiconductor layer (FIG. 2, item 180; [0037] i.e. The third conductive layer 180 is .. For example, WSix)
Park et al and Nam et al fails to explicitly disclose is formed of amorphous silicon.
However, Tamura et al teaches is formed of amorphous silicon (Column 17, [lines 39-43], i.e. without any crystal growth is used in the tungsten silicide film 3D of the bottom electrode 3F, so that the tungsten silicide film 3D is formed having an amorphous structure)
Since Park et al, Nam et al and Tamura et al teach electrodes comprising tungsten, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Park et al and Nam et al with the teachings of is formed of amorphous silicon as disclosed by Tamura et al. The use of without any crystal growth is used in the tungsten silicide film 3D of the bottom electrode 3F, so that the tungsten silicide film 3D is formed having an amorphous structure in Tamura et al provides for since no crystal grain field exists on the surface of the tungsten silicide film 3D accumulated under such conditions, the smoothness of the surface of the tungsten silicide film 3D is promoted (Tamura et al, [Column 17, lines 44-47]).
Regarding claim 31. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 13 above.
Name et al discloses the silicon semiconductor layer (FIG. 2, item 180; [0037] i.e. The third conductive layer 180 is .. For example, WSix)
Park et al and Nam et al fails to explicitly disclose is formed of amorphous silicon.
However, Tamura et al teaches is formed of amorphous silicon (Column 17, [lines 39-43], i.e. without any crystal growth is used in the tungsten silicide film 3D of the bottom electrode 3F, so that the tungsten silicide film 3D is formed having an amorphous structure)
Since Park et al, Nam et al and Tamura et al teach electrodes comprising tungsten, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Park et al and Nam et al with the teachings of is formed of amorphous silicon as disclosed by Tamura et al. The use of without any crystal growth is used in the tungsten silicide film 3D of the bottom electrode 3F, so that the tungsten silicide film 3D is formed having an amorphous structure in Tamura et al provides for since no crystal grain field exists on the surface of the tungsten silicide film 3D accumulated under such conditions, the smoothness of the surface of the tungsten silicide film 3D is promoted (Tamura et al, [Column 17, lines 44-47]).
Regarding claim 32. Park et al and Nam et al discloses all the limitations of the semiconductor memory device of claim 16 above.
Name et al discloses the silicon semiconductor layer (FIG. 2, item 180; [0037] i.e. The third conductive layer 180 is .. For example, WSix)
Park et al and Nam et al fails to explicitly disclose is formed of amorphous silicon.
However, Tamura et al teaches is formed of amorphous silicon (Column 17, [lines 39-43], i.e. without any crystal growth is used in the tungsten silicide film 3D of the bottom electrode 3F, so that the tungsten silicide film 3D is formed having an amorphous structure)
Since Park et al, Nam et al and Tamura et al teach electrodes comprising tungsten, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Park et al and Nam et al with the teachings of is formed of amorphous silicon as disclosed by Tamura et al. The use of without any crystal growth is used in the tungsten silicide film 3D of the bottom electrode 3F, so that the tungsten silicide film 3D is formed having an amorphous structure in Tamura et al provides for since no crystal grain field exists on the surface of the tungsten silicide film 3D accumulated under such conditions, the smoothness of the surface of the tungsten silicide film 3D is promoted (Tamura et al, [Column 17, lines 44-47]).
Response to Arguments
Applicant's arguments filed March 23, 2026 have been fully considered but they are not persuasive.
Prior art Rejections Under 35 U.S.C. 103.
On page 11 of applicant’s remarks, Applicant appears to argue that Nam et al does not disclose the silicon semiconductor layer of claim 1 because WSix is a conductor and not a silicon semiconductor layer, which provide the semiconductor functionality.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a silicon semiconductor layer, which provide the semiconductor functionality) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Examiner respectfully points out that Applicant’s claim 1 language does not require silicon semiconductor layer which provides semiconductor functionality. Examiner further points out, that dependent claim 5, requires wherein the silicon semiconductor layer does not include boron, while claim 1 states wherein the top electrode includes a first metal layer, a silicon-germanium semiconductor layer, a conductive adhesion layer, a second metal layer, and a silicon semiconductor layer that are sequentially stacked. Nam discloses WSix operates functionally as an electrode, as claimed by applicant. Regarding Applicant’s arguments that WSix is not a silicon semiconductor layer, Hoe et al ([0035]) and Dellasega et al ([56]) are used as evidence shows that WSix is a silicon semiconductor layer. Examiner respectfully points out that Dellasega also discloses as evidence a work function for the WSix which is indicative of the functionality of a semiconductor layer.
Applicant appears to further arguing the intended use of WSix in Nam rather than the structure.
Examiner respectfully points out that applicant has only claimed the structure of an electrode and has not claimed any use or functionality of a semiconductor layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Han et al (U.S. 2021/0210492) discloses a semiconductor memory device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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