Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 1/27/2026 have been fully considered but they are not persuasive.
Applicant argues that Examiner’s modification of Otremba would render Otremba “unstatisfactory for its intended purpose” and furthermore, would render the device of Otremba inoperable. Examiner disagrees for the following reasons.
First, in Examiner’s view, Otremba does not disclose one specific intended use for the device. In contrast, Otremba states “The embodiments of an electronic device and a method for fabricating an electronic device may use various types of semiconductor chips or circuits incorporated in the semiconductor chips, among them AC/DC or DC/DC converter circuits, power MOS transistors, power Schottky diodes, JFETs (Junction Gate Field Effect Transistors), power bipolar transistors, logic integrated circuits, analogue integrated circuits, mixed signal integrated circuits, sensor circuits, MEMS (Micro-Electro-Mechanical-Systems), power integrated circuits, chips with integrated passives, etc.” (Para. [0014] – bold added by Examiner for emphasis). Since Otremba mentions sensor circuits as one of the possible uses of the invention, Examiner sees no reason to limit the intended use of the any configuration to one where the contact clip must be electrically connected to the source/emitter. In fact, for a sensor circuit, as disclosed by Racz (Fig. 4), the clip is not directly contact the source/emitter.
Next, Applicant cites Otremba, who says “According to an embodiment all of parts 42-45 are electrically and thermally conductive. According to another embodiment at least one of parts 42-45 is thermally conductive but not electrically conductive. However, parts 42-45 are still configured such that an electrically conductive connection between first electrode 10A and first substrate element 20 exists.”. While Otremba may have been contemplating an electrical connection between the clip and source/emitter, Examiner is of the view that this does not preclude a severing of the electrical connection. While Otremba may have been contemplating an electrical connection between the source/emitter and the clip in this configuration, this does not mean that the embodiment can never be modified to break that connection. As discussed above, for a sensor, as in Racz, breaking the connection is possible, and still renders the circuit operable.
In summary, Examiner disagrees with Applicant’s arguments and is maintaining the 103 rejection of claims 20-21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over US20150214133A1 (Otremba1) in view of US20140333301A1 (Racz).
Regarding Claims 20 and 21, Otremba1 discloses a semiconductor component (Fig. 3A, el. 300), comprising: a chip carrier (Fig. 3A, el. 30, 20A, and 21A Para. [0045]); a semiconductor chip (Fig. 3A, el. 10, Para. [0045]) mounted on the chip carrier (Fig. 3A, Para. [0045])); a chip package (Fig. 3C, el. 50, Para. [0047]) made of potting compound (Para. [0047]) that only partially surrounds the semiconductor chip (Figs. 3C and 3D), such that at least part of an upper side of the semiconductor chip is not covered by the potting compound (Figs. 3C and 3D, the part of the semiconductor chip 10 that is covered by a clip 40 is not covered by the potting compound 50); and a clip (Fig. 3B, el. 40, Para. [0046]) mechanically connected to the upper side of the semiconductor chip (Fig. 3B, Paras. [0046]).
Otremba1 does not disclose that the clip is electrically insulated from a chip metallization on the upper side of the semiconductor chip and does not disclose that a dielectric layer is arranged between the clip and the chip metallization.
Racz discloses a semiconductor chip (Fig. 4, el. 10, Para. [0033]), a clip mechanically connected to a side of the semiconductor chip (Fig. 1 and 4, el. 5, Paras. [0027] and [0033]), wherein the clip is electrically insulated from a chip metallization by an insulator which is a dielectric layer (Fig. 4, el. 21, Para. [0033]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the clip disclosed by Otremba1, and add an insulating layer that is a dielectric layer between the clip and the chip metallization on the upper side of the semiconductor chip, as disclosed by Racz. As disclosed by Rasz, doing so would allow a sensor to be placed between the chip and the clip without the sensor being electrically connected to the clip (Fig. 1, Para. [0027]), while having a dielectric layer as the insulation layer can increase the dielectric strength between the chip and the clip (Para. [0033]). Although the insulation layer is on the opposite side in Racz, it would be a simple rearrangement of parts to move the insulation layer of Racz to the opposing side (see MPEP 2144.04 (VI)(C)).
Allowable Subject Matter
Claim 1-8 and 10-13 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination that the clip and the chip package are mechanically connected via a plug-in or snap-fit connection.
Claims 2-8 and 10-13 are allowed because they depend on Claim 1.
Claim 18 is allowed.
Regarding Claim 18, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination that the clip and the chip package have corresponding geometries that define a relative position of the clip with respect to the chip package when the clip rests against the chip package.
Claim 19 is allowed.
Regarding Claim 19, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination that a further semiconductor chip mounted on the chip carrier, wherein the clip is connected to a chip metallization of the semiconductor chip and a chip metallization of the further semiconductor chip.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899