DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to claims 1, 10 and 17 (and their dependent claims) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Accordingly dependent claims 14-16 will be allowed as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over JUNG; JONG-HOON (US PGpub: 2017/0098608 A1), herein after JUNG, in view of JUNG.
Regarding claim 1, JUNG teaches a semiconductor structure, comprising:
a first via-to-backside power rail (11, FIG. 11, 13) having a lower portion and an upper portion, the lower portion being connected to a first backside power rail (12) and having a first width and the upper portion having a second width less than the first width (as in the Fig. 11 or 13).
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JUNG does not explicitly teach a backside power delivery network disposed on the first backside power rail.
However it is interpretable that GPR (Above figure) area can be considered a power delivery network. A PDN ensures stable voltage and current supply to all active devices. The examiner believes that GPR does that and can be considered a PDN which is disposed on the first backside power rail (12).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use JUNG’s IC device with teachings from JUNG in order to reduce power rail resistance and increase capacitance, thereby reducing a drop in power supply voltage in order to form an efficient device.
Regarding claim 2, JUNG teaches the semiconductor structure of claim 1, wherein the lower portion of the first via-to- backside power rail is disposed in an interlevel dielectric layer (Lower portion disposed in AR1 as in FIG. 11).
Regarding claim 3, JUNG teaches the semiconductor structure of claim 2, further comprising a first source/drain region (near 354 in FIG. 13) and a second source/drain region (near 352 in FIG. 13) disposed on the interlevel dielectric layer (AR1); wherein the upper portion of the first via-to-backside power rail is disposed between the first source/drain region and the second source/drain region (part of the upper portion of first via-to-backside power rail is disposed between 354 and 352).
Regarding claim 4, JUNG teaches the semiconductor structure of claim 3, further comprising a first self-aligned spacer (as marked in above Figure) separating the upper portion of the first via-to-backside power rail from the first source/drain region and the second source/drain region (spacer is separating 354 and 352).
Regarding claim 5, JUNG teaches the semiconductor structure of claim 4, further comprising: a second backside power rail (12); and a second via-to-backside power rail having a lower portion (marked below) and an upper portion (marked below), the lower portion being connected to the second backside power rail and having a first width and the upper portion having a second width less than the first width (as in the Fig. 11 or 13).
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Regarding claim 6, JUNG teaches the semiconductor structure of claim 5, wherein the lower portion of the second via-to- backside power rail is disposed in the interlevel dielectric layer (AR2) (as above FIG.)
Regarding claim 7, JUNG teaches the semiconductor structure of claim 6 further comprising a third source/drain region (355 is the contact) and a fourth source/drain region (356) disposed on the interlevel dielectric layer; wherein the upper portion of the second via-to-backside power rail is disposed between the third source/drain region and the fourth source/drain region (as above FIG.).
Regarding claim 8, JUNG teaches the semiconductor structure of claim 7, further comprising a second self-aligned spacer separating the upper portion of the second via-to-backside power rail from the third source/drain region and the fourth source/drain region.
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Regarding claim 9, JUNG teaches the semiconductor structure of claim 8, wherein the first source/drain region (near 354, FIG. 13) and the second source/drain region (near 352, FIG. 13) are an n-type region and the third source/drain region (near 355) and the fourth source/drain region (near 356, FIG. 13) a p-type region (Paragraph [0050]).
Regarding claim 17, JUNG teaches a semiconductor structure, comprising:
a via-to-backside power rail (11) having a lower portion (as marked) and an upper portion, the lower portion (as marked) being connected to a backside power rail (as in FIG. 13) and having a first width and the upper portion having a second width less than the first width (as in the Fig. 11 or 13); and a middle-of-the-line contact (361) disposed on the upper portion of the via-to-backside power rail (11).
JUNG does not explicitly teach a backside power delivery network disposed on the first backside power rail.
However it is interpretable that GPR (Above figure) area can be considered a power delivery network. A PDN ensures stable voltage and current supply to all active devices. The examiner believes that GPR does that and can be considered a PDN which is disposed on the first backside power rail (12).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use JUNG’s IC device with teachings from JUNG in order to reduce power rail resistance and increase capacitance, thereby reducing a drop in power supply voltage in order to form an efficient device.
Regarding claim 18, JUNG teaches the semiconductor structure of claim 17, further comprising a self-aligned spacer disposed on sidewalls of the upper portion of the via-to-backside power rail and the middle-of-the- line contact (as marked in above FIG).
Regarding claim 19, JUNG teaches the semiconductor structure of claim 18, further comprising a dielectric pillar (22 in gate line which includes G1 in FIG. 14) disposed on sidewalls of the self-aligned spacer.
Regarding claim 20, JUNG teaches the semiconductor structure of claim 17, further comprising a frontside back-end-of- line interconnect (MG1 in FIG. 14) disposed on the middle-of-the-line contact.
Claims 10-12 is rejected under 35 U.S.C. 103 as being unpatentable over JUNG; JONG-HOON (US PGpub: 2017/0098608 A1), herein after JUNG, in view of JUNG.
Regarding claim 10, JUNG teaches a semiconductor structure, comprising:
a first via-to-backside power rail (11) having a lower portion, a middle portion and an upper portion, the lower portion disposed in an interlevel dielectric layer (Part of the lower portion is disposed in interlevel dielectric layer (AR1));
a first backside power rail (12) connected to the lower portion of the first via-to-backside power rail (it is connected); and a first source/drain region (near 354 in FIG. 13) and a second source/drain region (near 352 in FIG. 13) disposed on the interlevel dielectric layer (AR1);
wherein the lower portion has a first width and the middle portion has a second width (lower portion has a width and middle potion has another width);
wherein the middle portion is disposed between the first source/drain region and the second source/drain region (as middle portion is disposed between 354 and 352); and wherein the upper portion is disposed on a portion of a sidewall of the first source/drain region (connected to upper sidewall. Hence, it is inferred that upper portion is disposed on top of the sidewall of the source/drain region) to connect the middle portion to the first source/drain region (near 354).
JUNG does not explicitly teach the lower portion has a first width and the middle portion has a second width less than the first width. JUNG also does not explicitly teach a backside power delivery network disposed on the first backside power rail.
However it is interpretable how you define the middle portion. If you consider the middle portion is the portion between 23 and 24, then middle portion width is less than lower portion as in FIG. 13 of JUNG (width direction has to be explicitly mentioned in the claims, otherwise width direction is subject to interpretation. If you consider width in the horizontal direction, middle portion width is less than that of lower portion). Also, it is interpretable that GPR (Above figure) area can be considered a power delivery network. A PDN ensures stable voltage and current supply to all active devices. The examiner believes that GPR does that and can be considered a PDN which is disposed on the first backside power rail (12).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use JUNG’s IC device with teachings from JUNG in order to reduce power rail resistance and increase capacitance, thereby reducing a drop in power supply voltage in order to form an efficient device.
Regarding claim 11, JUNG teaches the semiconductor structure of claim 10, further comprising: a first self-aligned spacer (as spacer in below FIG) disposed on the remaining portion of the sidewall of the first source/drain region (near 354 in FIG. 13), wherein the first self-aligned spacer and the upper portion of the first via-to- backside power rail separate the middle portion of the first via-to-backside power rail from the first source/drain region (as in FIG. 13); and a second self-aligned spacer (201) disposed on a sidewall of the second source/drain region (near 352 in FIG. 13) to separate the middle portion of the first via-to-backside power rail from the second source/drain region.
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Regarding claim 12, JUNG teaches the semiconductor structure of claim 11, further comprising: a first source/drain contact (354) disposed on the first source/drain region (near 354 in FIG. 13) and upper portion of the first via-to-backside power rail; and a second source/drain contact (352) disposed on the second source/drain region (near 352 in FIG. 13).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
Prosecution Insights