Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/28/2026 and 03/05/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-36 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-36 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 10, 19 and 28 of copending Application No. 17/955,110 in view of Munshi (US 10067797 B2) in view of Goodman (US 11204774 B1).
This is a provisional nonstatutory double patenting rejection.
17/955,110
17/955,094
Claim 1. One or more processors
Claim 1. One or more processors
Claim 2. The one or more processors claim 1, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads of the software kernel that can be concurrently performed on the accelerator.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 3. The one or more processors claim 1, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 4. The one or more processors claim 1, wherein the maximum number is a limit on the number of groups of blocks of threads.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 5. The one or more processors of claim 1, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads that can be concurrently performed on the accelerator.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 6. The one or more processors claim 1, wherein the maximum number is based, at least in part, on an architecture of the accelerator.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below teachings of Marrow and Munshi to coordinate thread allocation, see art rejection below.
Claim 7 . The one or more processors claim 1, wherein the API is to return the maximum number.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below.
Claim 8 . The one or more processors claim 1, wherein the API is to cause the accelerator to perform the maximum number of groups.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 9 . The one or more processors claim 1, wherein the API is to return a number of partitions of blocks of a grid of blocks of threads.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 10. A computer-implemented method comprising: receiving an application programming interface (API) call comprising one or more parameters indicating a software kernel to be performed on an accelerator; and in response to receiving the API call, indicating a maximum number of groups of blocks of threads capable of being performed in parallel within the indicated kernel, wherein at least one group of the groups of blocks of threads comprises multiple blocks of threads.
Claim 10 . A computer-implemented method comprising: indicating, in response to a call to an application programming interface (API), a maximum number of blocks of threads of a software kernel to be performed on a graphics processing unit (GPU), wherein the maximum number of blocks is a limit of a number of groups of blocks of threads of a software kernel. in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below.
Claim 11 . The computer-implemented method of claim 10, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads of the software kernel that can be concurrently performed on the accelerator.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 12. The computer-implemented method of claim 10, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 13. The computer-implemented method of claim 10, wherein the maximum number the maximum number is a limit on a number of groups of blocks of threads.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 14. The computer-implemented method of claim 10, wherein the maximum number indicates a maximum cluster size capable of being performed concurrently by a GPU
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 15. The computer-implemented method of claim 10, wherein the maximum number is based, at least in part, on an architecture of the accelerator.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 16. The computer-implemented method of claim 10, wherein the API is to return the maximum number.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 17. The computer-implemented method of claim 10,
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further comprising in response to receiving the API call, causing the maximum number to be applied.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 18 . The computer-implemented method of claim 10, further comprising: in response to receiving the API call, returning a number of partitions of blocks of a grid of blocks.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 19. A computer system comprising: one or more processors and memory storing executable instructions that, if performed by the one or more processors, are to cause the one or more processors to, in response to an application programming interface (API) call, return an indication of a maximum number of groups of blocks of threads of a software kernel capable of being performed concurrently on an accelerator, wherein at least one group of the groups of blocks of threads comprises multiple blocks of threads.
Claim 19. A computer system comprising: one or more processors and memory storing executable instructions that, if performed by the one or more processors, are to in response to a call to an application programming interface (API) indicate a maximum number of blocks of threads of a software kernel to be performed on a graphics processing unit (GPU), wherein the maximum number of blocks is a limit of a number of groups of blocks of threads of a software kernel. in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below.
Claim 20. The computer system of claim 19, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads of the software kernel that can be concurrently performed on the accelerator.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 21. The computer system of claim 19, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 22. The computer system of claim 19, wherein the maximum number is a limit on number of groups of blocks of threads .
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 23 . The computer system of claim 19, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads that can be concurrently performed on the accelerator.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 24 . The computer system of claim 19, wherein the maximum number is based, at least in part, on an architecture of the accelerator.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 25 . The computer system of claim 19, wherein the API is to return the maximum number.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 26 . The computer system of claim 19, wherein the API is to cause the accelerator to perform the maximum number of groups
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 27 . The computer system of claim 19, wherein the API is to return a number of partitions of blocks of a grid of blocks of threads.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 28 . A non-transitory machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, are to cause the one or processors to,
Claim 28 . A non-transitory machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, are to in response to a call to an application programming interface (API),
Claim 29 . The non-transitory machine-readable medium of claim 28, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads of the software kernel that can be concurrently performed on the accelerator.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 30 . The non-transitory machine-readable medium of claim 28, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 31 . The non-transitory machine-readable machine-readable medium of claim 28, wherein the maximum number the maximum number is a limit a number of groups of blocks of threads.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 32 . The non-transitory machine-readable medium of claim 28, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads that can be concurrently performed on the accelerator.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 33 . The non-transitory machine-readable medium of claim 28, wherein the maximum number is based, at least in part, on an architecture of an accelerator-a graphics processing unit (GPU).
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 34 The non-transitory machine-readable medium of claim 28, wherein the API is to return the maximum number.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 35 . The non-transitory machine-readable medium of claim 28, wherein the API is to cause the accelerator to perform the maximum number of groups.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 36 . non-transitory machine-readable medium of claim 28, wherein the API is to return a number of partitions of blocks of a grid of blocks of threads.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 1-36 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 10, 19 and 28 of copending Application No. 17/955,123 in view of Munshi (US 10067797 B2) in view of Goodman (US 11204774 B1).
This is a provisional nonstatutory double patenting rejection.
17/955,110
17/955,123
Claim 1. One or more processors
Claim 1. One or more processors, comprising: circuitry to: in response to a call to an application programming interface (API) comprising parameters indicative of a cluster of two or more groups of blocks of threads, cause a kernel to be performed by at least scheduling the cluster comprising the two or more groups of blocks of threads to be performed in parallel, wherein each group of blocks of threads comprises one or more blocks of threads and each block of threads comprises two or more threads. In view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Marrow and Munshi to coordinate thread allocation, see art rejection below.
Claim 2. The one or more processors claim 1, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads of the software kernel that can be concurrently performed on the accelerator.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 3. The one or more processors claim 1, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 4. The one or more processors claim 1, wherein the maximum number is a limit on the number of groups of blocks of threads.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 5. The one or more processors of claim 1, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads that can be concurrently performed on the accelerator.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 6. The one or more processors claim 1, wherein the maximum number is based, at least in part, on an architecture of the accelerator.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below teachings of Marrow and Munshi to coordinate thread allocation, see art rejection below.
Claim 7 . The one or more processors claim 1, wherein the API is to return the maximum number.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below.
Claim 8 . The one or more processors claim 1, wherein the API is to cause the accelerator to perform the maximum number of groups.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 9 . The one or more processors claim 1, wherein the API is to return a number of partitions of blocks of a grid of blocks of threads.
Claim 1 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 10. A computer-implemented method comprising: receiving an application programming interface (API) call comprising one or more parameters indicating a software kernel to be performed on an accelerator; and in response to receiving the API call, indicating a maximum number of groups of blocks of threads capable of being performed in parallel within the indicated kernel, wherein at least one group of the groups of blocks of threads comprises multiple blocks of threads.
Claim 10 . A computer-implemented method comprising: in response to a call to an application programming interface (API) comprising parameters indicative of a cluster of two or more groups of blocks of threads, performing a kernel by at least scheduling the cluster comprising the two or more groups of blocks of threads to be performed in parallel, wherein each group of blocks of threads comprises one or more blocks of threads and each block of threads comprises two or more threads. in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below.
Claim 11 . The computer-implemented method of claim 10, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads of the software kernel that can be concurrently performed on the accelerator.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 12. The computer-implemented method of claim 10, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 13. The computer-implemented method of claim 10, wherein the maximum number the maximum number is a limit on a number of groups of blocks of threads.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 14. The computer-implemented method of claim 10, wherein the maximum number indicates a maximum cluster size capable of being performed concurrently by a GPU
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 15. The computer-implemented method of claim 10, wherein the maximum number is based, at least in part, on an architecture of the accelerator.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 16. The computer-implemented method of claim 10, wherein the API is to return the maximum number.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 17. The computer-implemented method of claim 10,
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further comprising in response to receiving the API call, causing the maximum number to be applied.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 18 . The computer-implemented method of claim 10, further comprising: in response to receiving the API call, returning a number of partitions of blocks of a grid of blocks.
Claim 10 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 19. A computer system comprising: one or more processors and memory storing executable instructions that, if performed by the one or more processors, are to cause the one or more processors to, in response to an application programming interface (API) call, return an indication of a maximum number of groups of blocks of threads of a software kernel capable of being performed concurrently on an accelerator, wherein at least one group of the groups of blocks of threads comprises multiple blocks of threads.
Claim 19. A computer system comprising: one or more processors and memory storing executable instructions that, when performed by the one or more processors, are to. in response to a call to an application programming interface (API) comprising parameters indicative of a cluster of two or more groups of blocks of threads, cause a kernel to be performed by at least scheduling the cluster comprising the two or more groups of blocks of threads to be performed in parallel, wherein each group of blocks of threads comprises one or more blocks of threads and each block of threads comprises two or more threads. in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below.
Claim 20. The computer system of claim 19, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads of the software kernel that can be concurrently performed on the accelerator.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 21. The computer system of claim 19, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 22. The computer system of claim 19, wherein the maximum number is a limit on number of groups of blocks of threads .
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 23 . The computer system of claim 19, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads that can be concurrently performed on the accelerator.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 24 . The computer system of claim 19, wherein the maximum number is based, at least in part, on an architecture of the accelerator.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 25 . The computer system of claim 19, wherein the API is to return the maximum number.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 26 . The computer system of claim 19, wherein the API is to cause the accelerator to perform the maximum number of groups
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 27 . The computer system of claim 19, wherein the API is to return a number of partitions of blocks of a grid of blocks of threads.
Claim 19 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 28 . A non-transitory machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, are to cause the one or processors to,
Claim 28 . A non-transitory machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, are to: in response to a call to an application programming interface (API) comprising parameters indicative of a cluster of two or more groups of blocks of threads, cause a kernel to be performed by at least scheduling the cluster comprising the two or more groups of blocks of threads to be performed in parallel, wherein each group of blocks of threads comprises one or more blocks of threads and each block of threads comprises two or more threads.. in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below.
Claim 29 . The non-transitory machine-readable medium of claim 28, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads of the software kernel that can be concurrently performed on the accelerator.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 30 . The non-transitory machine-readable medium of claim 28, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 31 . The non-transitory machine-readable machine-readable medium of claim 28, wherein the maximum number the maximum number is a limit a number of groups of blocks of threads.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 32 . The non-transitory machine-readable medium of claim 28, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads that can be concurrently performed on the accelerator.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 33 . The non-transitory machine-readable medium of claim 28, wherein the maximum number is based, at least in part, on an architecture of an accelerator-a graphics processing unit (GPU).
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 34 The non-transitory machine-readable medium of claim 28, wherein the API is to return the maximum number.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 35 . The non-transitory machine-readable medium of claim 28, wherein the API is to cause the accelerator to perform the maximum number of groups.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim 36 . non-transitory machine-readable medium of claim 28, wherein the API is to return a number of partitions of blocks of a grid of blocks of threads.
Claim 28 in view of Munshi and Goodman. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munshi and Goodman to coordinate thread allocation, see art rejection below
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-36 are rejected under 35 U.S.C. 103 as being unpatentable over Munshi (US 10067797 B2) in view of Goodman (US 11204774 B1).
Regarding claim 1, Munshi teaches:
One or more processors comprising: circuitry to: (col 3, line 23-27. The processes depicted in the figures that follow, are performed by processing logic that comprises hardware (e.g., circuitry, dedicated logic, etc.), software (such as is run on a general-purpose computer system or a dedicated machine), or a combination of both.)
in response to an application programming interface (API) call, return an indication of a maximum number of groups of blocks of threads of a software kernel capable of being performed concurrently on an accelerator, (col 5, line 4-14. An application 103 may interface with other stack components through API calls. One or more threads may be running concurrently for the application 103 in the hosting systems 101. The compute platform layer 111 may maintain a data structure, or a computing device data structure, storing processing capabilities for each attached physical computing device. In one embodiment, an application may retrieve information about available processing resources of the hosting systems 101 through the compute platform layer 111. An application 103 may interface with other stack components through API calls. One or more threads may be running concurrently for the application 103 in the hosting systems 101. The compute platform layer 111 may maintain a data structure, or a computing device data structure, storing processing capabilities for each attached physical computing device. In one embodiment, an application may retrieve information about available processing resources of the hosting systems 101 through the compute platform layer 111. Table 2, Col 9, lines 1-66 CL_DEVICE_MAX_COMPUTE_UNITS The number of parallel compute units on the computing device. The minimum value is one. Col 6, line 32-45. FIG. 2 is a block diagram illustrating an example of a computing device with multiple compute processors (e.g. compute units) operating in parallel to execute multiple threads concurrently. Each compute processor may execute a plurality of threads in parallel (or concurrently). Threads that can be executed in parallel in a compute processor or compute unit may be referred to as a thread group. A computing device could have multiple thread groups that can be executed in parallel. For example, M threads are shown to execute as a thread group in computing device 205. Multiple thread groups, e.g. thread 1 of compute processor_1 205 and thread N of compute processor_L 203, may execute in parallel across separate compute processors on one computing device or across multiple computing devices. )
Munshi does not appear to explicitly teach: wherein at least one group of the groups of blocks of threads comprises multiple blocks of threads.
However, Goodman teaches: col 4, line 18-50. The term “SIMD group” is intended to be interpreted according to its well-understood meaning, which includes a set of threads for which processing hardware processes the same instruction in parallel using different input data for the different threads. Various types of computer processors may include sets of pipelines configured to execute SIMD instructions. For example, graphics processors often include programmable shader cores that are configured to execute instructions for a set of related threads in a SIMD fashion. Other examples of names often used for a SIMD group include: a wavefront, a clique, or a warp. A SIMD group may be a part of a larger thread group, which may be broken up into a number of SIMD groups based on the parallel processing capabilities of a computer. In some embodiments, each thread is assigned to a hardware pipeline that fetches operands for that thread and performs the specified operations in parallel with other pipelines for the set of threads. Note that processors may have a large number of pipelines such that multiple separate SIMD groups may also execute in parallel. In some embodiments, each thread has private operand storage, e.g., in a register file. Thus, a read of a particular register from the register file may provide the version of the register for each thread in a SIMD group. As used herein, the term “thread” includes its well-understood meaning in the art and refers to sequence of program instructions that can be scheduled for execution independently of other threads. Multiple threads may be included in a SIMD group to execute in lock-step. Multiple threads may be included in a task or process (which may correspond to a computer program). Threads of a given task may or may not share resources such as registers and memory. Thus, context switches may or may not be performed when switching between threads of the same task.
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement the API based thread group execution of Munshi in the known structure of Goodman. Goodman teaches a large thread group maybe broken into multiple SIMD groups and that multiple SIMD groups may execute in parallel. A person of ordinary skill in the art would have found it obvious to implement Munshi’s API in a system like Goodman’s provides a known hardware execution structure for grouped threads.
Regarding claim 2, Munshi teaches:
The one or more processors of claim 1, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads of the software kernel that can be concurrently performed on the accelerator. (col 18, line 38- col 19, line 11. FIG. 8 is a flow diagram illustrating one embodiment of a process 800 to determine optimal thread group sizes to concurrently execute compute kernel objects among multiple compute units. Exemplary process 800 may be performed by a processing logic that may comprise hardware (circuitry, dedicated logic, etc.), software (such as is run on a dedicated machine), or a combination of both. For example, process 800 may be performed by some components of system 100 of FIG. 1 or as part of process 500 at block 523 of FIG. 5. In one embodiment, at block 801 the processing logic of process 800 may determine resource requirements from executable codes compiled from a single source targeting different compute units. Resource requirements of an executable code may include usage data on registers, memories and/or other hardware components for a target compute unit for the executable code. A single source may be compiled into different executable codes loaded into different types of compute units to perform a data parallel task (or function) specified by the single source. In some embodiments, the processing logic of process 800 may determine resource requirements based on a source code and a target compute unit for executing instructions compiled from the source code. The processing logic of process 800 may analyze (and/or traverse) an intermediate representation of executable codes compiled from a source code targeting a compute unit to determine required resources to execute the executable codes in the target compute unit. During the analysis, the processing logic of process 800 may identify a portion of a source code based on matching optimization conditions to recompile the identified portion of the source code to reduce the required resources for execution in the target compute unit. For example, the processing logic of process 800 may replace a variable in a source code with a constant value The processing logic of process 800 may identify a dimension of a data parallel task according to an analysis of the corresponding executable codes. When an identified dimension differs from a dimension specified, for example, using APIs, the processing logic of process 800 may select one of the identified dimension and the specified dimension according to, for example, a system setting. See also TABLE 2 )
Regarding claim 3, Munshi teaches:
The one or more processors of claim 1, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads. (col 19, line 4-20. The processing logic of process 800 may identify a dimension of a data parallel task according to an analysis of the corresponding executable codes. When an identified dimension differs from a dimension specified, for example, using APIs, the processing logic of process 800 may select one of the identified dimension and the specified dimension according to, for example, a system setting. At block 803, in some embodiment, the processing logic of process 800 may determine optimal thread group sizes for executing executable codes in parallel among multiple compute units according to the determined resource requirements. A group of threads may execute an executable code compiled concurrently in a target compute unit. An optimal thread group size may be the number of threads in a thread group to execute an executable code in a compute unit to maximize resource usage within the compute unit. See also TABLE 2)
Regarding claim 4, Munshi teaches:
The one or more processors of claim 1, wherein the maximum number is a limit on the number of groups of blocks of threads. (Table 2 CL_DEVICE_MAX_COMPUTE_UNITS The number of parallel compute units on the computing device. The minimum value is one. Col 6, line 32-45. FIG. 2 is a block diagram illustrating an example of a computing device with multiple compute processors (e.g. compute units) operating in parallel to execute multiple threads concurrently. Each compute processor may execute a plurality of threads in parallel (or concurrently). Threads that can be executed in parallel in a compute processor or compute unit may be referred to as a thread group. A computing device could have multiple thread groups that can be executed in parallel. For example, M threads are shown to execute as a thread group in computing device 205. Multiple thread groups, e.g. thread 1 of compute processor_1 205 and thread N of compute processor_L 203, may execute in parallel across separate compute processors on one)
Regarding claim 5, Munshi teaches:
The one or more processors of claim 1, wherein the maximum number is a limit on a number of partitions of blocks of threads of a grid of blocks of threads that can be concurrently performed on the accelerator. (col 6, line 33-52. FIG. 2 is a block diagram illustrating an example of a computing device with multiple compute processors (e.g. compute units) operating in parallel to execute multiple threads concurrently. Each compute processor may execute a plurality of threads in parallel (or concurrently). Threads that can be executed in parallel in a compute processor or compute unit may be referred to as a thread group. A computing device could have multiple thread groups that can be executed in parallel. For example, M threads are shown to execute as a thread group in computing device 205. Multiple thread groups, e.g. thread 1 of compute processor_1 205 and thread N of compute processor_L 203, may execute in parallel across separate compute processors on one computing device or across multiple computing devices. A plurality of thread groups across multiple compute processors may execute a compute program executable in parallel. More than one compute processors may be based on a single chip, such as an ASIC (Application Specific Integrated Circuit) device. In one embodiment, multiple threads from an application may be executed concurrently in more than one compute processors across multiple chips.)
Regarding claim 6, Munshi teaches:
The one or more processors of claim 1, wherein the maximum number is based, at least in part, on an architecture of the accelerator. (col 14, line 46-65. In one embodiment, a compute program executable may include description data associated with, for example, the type of target physical computing devices (e.g. a GPU or a CPU), versions, and/or compilation options or flags, such as a thread group sizes and/or thread group dimensions. A compute program source may be the source code where a compute program executable is compiled from. The processing logic of process 500 may load multiple compute program executables corresponding to a compute program source at block 509. In one embodiment, the processing logic of process 500 may load a compute program executable from an application or through a compute library such as compute application library 105 of FIG. 1. A compute program executable may be loaded with the corresponding compute program source. The processing logic of process 500 may set up function arguments for a compute program object at block 505. In one embodiment, the processing logic of process 500 may perform operations at blocks 503, 505 and 509 according to API requests from an application.)
Regarding claim 7, Munshi teaches:
The one or more processors of claim 1, wherein the API is to return the maximum number. (col 19, line 38-51. The processing logic of process 800 may receive an API request from an application running in a host processor (or host processing unit), such as applications 103 in hosting systems 101 of FIG. 1. An API request may include a global thread number having a multi-dimensional value as an array of N integers (G.sub.1, G.sub.2, . . . , G.sub.N). Integer N may be a dimension associated with the data parallel task. The processing logic of process 800 may count the number of integers in an array from a multi-dimensional value to determine a dimension. In response to the API request, the processing logic of process 800 may determine the total number of threads that will execute the executable codes among the multiple compute units according to a product of N integers as G.sub.1*G.sub.2* . . . *G.sub.N.)
Regarding claim 8, Munshi teaches:
The one or more processors of claim 1, wherein the API is to cause the accelerator to perform the maximum number of groups. (col 18, line 4-37. At block 703, in one embodiment, process 700 may select a compute kernel execution instances for execution from multiple scheduled compute kernel execution instances without any outstanding dependency condition. The selection may be based on a priority level assigned to an execution instance. In one embodiment, the selected compute kernel execution instance may be associated the highest priority level among the plurality of compute kernel execution instances without outstanding dependency conditions. At block 705, process 700 may retrieve a current execution statues for one or more of the physical computing devices corresponding to the selected compute kernel execution instance. In one embodiment, execution status of a physical computing device may be retrieved from predetermined memory locations. In another embodiment, process 700 may send a status request to a physical computing device to receive an execution status report. Process 700 may designate one or more of the physical computing devices to execute the selected compute kernel execution instance based on the retrieved execution statuses at block 707. In one embodiment, a physical computing device may be designated for execution according to a load balancing consideration with other physical computing devices. The selected physical computing device may be associated with an execution status satisfying one or more specified (e.g. predetermined) criteria, such as below a predetermined processor usage level and/or memory usage level. In one embodiment, the predetermined criteria may depend on the number of threads and the number of thread groups associated with the selected compute kernel execution instance. Process 700 may load separate compute kernel executables for the same execution instance or multiple instances to one or more designated physical computing devices to execute in parallel in multiple threads.)
Regarding claim 9, Munshi teaches:
The one or more processors of claim 1, wherein the API is to return a number of partitions of blocks of a grid of blocks of threads. (Table 2 CL_DEVICE_MAX_COMPUTE_UNITS The number of parallel compute units on the computing device.)
Regarding claim 10, Munshi teaches:
A computer-implemented method comprising.( Claim 1. A computerized method comprising)
the claim recites similar limitation as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale.
Regarding claim 11 the claim recites similar limitation as corresponding claim 2 and is rejected for similar reasons as claim 2 using similar teachings and rationale.
Regarding claim 12 the claim recites similar limitation as corresponding claim 3 and is rejected for similar reasons as claim 3 using similar teachings and rationale.
Regarding claim 13 the claim recites similar limitation as corresponding claim 4 and is rejected for similar reasons as claim 4 using similar teachings and rationale.
Regarding claim 14 the claim recites similar limitation as corresponding claim 5 and is rejected for similar reasons as claim 5 using similar teachings and rationale.
Regarding claim 15 the claim recites similar limitation as corresponding claim 6 and is rejected for similar reasons as claim 6 using similar teachings and rationale.
Regarding claim 16 the claim recites similar limitation as corresponding claim 7 and is rejected for similar reasons as claim 7 using similar teachings and rationale.
Regarding claim 17 the claim recites similar limitation as corresponding claim 8 and is rejected for similar reasons as claim 8 using similar teachings and rationale.
Regarding claim 18 the claim recites similar limitation as corresponding claim 9 and is rejected for similar reasons as claim 9 using similar teachings and rationale.
Regarding claim 19, Marrow teaches:
A computer system comprising.( [0009] According to the present invention, there is provided a method or system as set out in the accompanying claims. Further inventive aspects of the invention are described below and set out in the drawings.)
the claim recites similar limitation as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale.
Regarding claim 20 the claim recites similar limitation as corresponding claim 2 and is rejected for similar reasons as claim 2 using similar teachings and rationale.
Regarding claim 21 the claim recites similar limitation as corresponding claim 3 and is rejected for similar reasons as claim 3 using similar teachings and rationale.
Regarding claim 22 the claim recites similar limitation as corresponding claim 4 and is rejected for similar reasons as claim 4 using similar teachings and rationale.
Regarding claim 23 the claim recites similar limitation as corresponding claim 5 and is rejected for similar reasons as claim 5 using similar teachings and rationale.
Regarding claim 24 the claim recites similar limitation as corresponding claim 6 and is rejected for similar reasons as claim 6 using similar teachings and rationale.
Regarding claim 25 the claim recites similar limitation as corresponding claim 7 and is rejected for similar reasons as claim 7 using similar teachings and rationale.
Regarding claim 26 the claim recites similar limitation as corresponding claim 8 and is rejected for similar reasons as claim 8 using similar teachings and rationale.
Regarding claim 27 the claim recites similar limitation as corresponding claim 9 and is rejected for similar reasons as claim 9 using similar teachings and rationale.
Regarding claim 28, Munshi teaches:
A machine-readable medium having stored thereon a set of instructions. (col 3, line 23-27. The processes depicted in the figures that follow, are performed by processing logic that comprises hardware (e.g., circuitry, dedicated logic, etc.), software (such as is run on a general-purpose computer system or a dedicated machine), or a combination of both.)
the claim recites similar limitation as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale.
Regarding claim 29 the claim recites similar limitation as corresponding claim 2 and is rejected for similar reasons as claim 2 using similar teachings and rationale.
Regarding claim 30 the claim recites similar limitation as corresponding claim 3 and is rejected for similar reasons as claim 3 using similar teachings and rationale.
Regarding claim 31 the claim recites similar limitation as corresponding claim 4 and is rejected for similar reasons as claim 4 using similar teachings and rationale.
Regarding claim 32 the claim recites similar limitation as corresponding claim 5 and is rejected for similar reasons as claim 5 using similar teachings and rationale.
Regarding claim 33 the claim recites similar limitation as corresponding claim 6 and is rejected for similar reasons as claim 6 using similar teachings and rationale.
Regarding claim 34 the claim recites similar limitation as corresponding claim 7 and is rejected for similar reasons as claim 7 using similar teachings and rationale.
Regarding claim 35 the claim recites similar limitation as corresponding claim 8 and is rejected for similar reasons as claim 8 using similar teachings and rationale.
Regarding claim 36 the claim recites similar limitation as corresponding claim 9 and is rejected for similar reasons as claim 9 using similar teachings and rationale.
Conclusion
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/C.A.E./Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199
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