Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 12/29/2025.
Claims 1-20 are currently pending.
Claims 1 and 7 have been amended.
Claims 13-20 have been withdrawn.
Claims 1-12 have been examined.
Election/Restriction
Applicant’s election without traverse of 1-12 of Group I in the reply filed on 12/29/2025 is acknowledged. Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang US 20230068625 A1 (hereinafter Wang) in view of Chang US 20150171081 A1 (herein after Chang).
Regarding claim 1, Wang discloses:
An integrated circuit (IC) die, (Wang, Fig. 20) comprising:
a first layer (Fig. 20, layer including dielectric material 320, conductive feature 330, and bonding layer 170.) with one or more conductive structures (conductive feature 330) in a first interlayer dielectric material, (dielectric material 320).)
with at least a portion of the one or more conductive structures at a first surface of the first layer; (See Fig. 20.)
a self-alignment layer in contact with non-conductive regions at the first surface of the first layer; (Fig. 19 and Fig. 20, second dielectric layer 340, first etch stop layer 360 and opening 390, where second dielectric layer 340 in contact with dielectric materials 320.)
a second layer with second interlayer dielectric material in contact with the self-alignment layer and the portion of the one or more conductive structures at the first surface of the first layer; and (See Fig. 20, third dielectric layer 380 in contact with the second dielectric layer 340 and portion 372 is in contact with conductive feature 330 which goes through the opening 390. The third dielectric layer 380 is also in indirect contact with contact feature 332.)
one or more conductive vias through the self-alignment layer and the second layer in respective contact with the portion of the one or more conductive structures at the first surface of the first layer, (See Fig. 10, conductive via 400.)
wherein the self-alignment layer comprises a first material where the self-alignment layer is in contact with the one or more conductive vias (Fig. 20, second dielectric layer 340 is in contact with conductive via 400.) and …
Wang does disclose a second material in the self-alignment layer such as etch stop layer 360 which is made from a high-k dielectric material ([0060]). While, the etch stop layer 360 does not contact conductive via 330, it does contact conductive via 332. Therefore, Wang does not appear to disclose where the second material of the self-alignment layer “is not in contact with the one or more conductive vias.”
Chang, which teaches a method of self-alignment of two more layers (Chang, Abstract), discloses having a spacers 114 which are in the self-alignment layer (Embodiment 1 shown in Figs. 1A- 1N, specifically Fig. 1C, layer which includes ILD 116 and the alignment structure 112 and spacers 114.) The spacer 114 is made of the same material as spacers 108. ([0024]) The spacer is made of silicon oxynitride (SiON, [0021]) which is a known high-k dielectric. (Wang discloses silicon oxynitride as high-k dielectric. Wang, [0021].) This is made of different material the ILD 116 layer which is made of low-k dielectric. (Chang, [0023]) Therefore the device made by the combination of Wang and Chang would have resulted in a device with predictable characteristics as described by the claimed invention. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang to have second material of the self-alignment layer is not in contact with the one or more conductive vias as taught by Chang for purposes of The ILD layer is able to be kept clean and fee of residue from other alignment structures that are formed in the ILD layer. (Chang, [0039].)
Regarding claim 2, Wang as modified by Chang disclose the elements of claim 1.
Wang further discloses:
wherein the first material of the self-alignment layer comprises a low-k material ([0054], second dielectric layer 340 is a low-k dielectric material. Therefore would have a dielectric constant lower than 3.9.)
Chang further discloses:
the second material of the self-alignment layer comprises a high- k material. (The spacer 114 is made of the same material as spacers 108. ([0024]) The spacer is made of silicon oxynitride which is a known high-k dielectric. (Wang discloses silicon oxynitride as high-k dielectric.) Therefore would have a dielectric constant higher than 3.9.)
Regarding claim 3, Wang as modified by Chang disclose the elements of claim 1.
Wang further discloses:
wherein a first dielectric constant of the first material of the self-alignment layer ([0054], second dielectric layer 340 is a low-k dielectric material.)
Chang further discloses:
a second dielectric constant of the second material of the self-alignment layer. (The spacer 114 is made of the same material as spacers 108. ([0024]) The spacer is made of silicon oxynitride which is a known high-k dielectric. (Wang discloses silicon oxynitride as high-k dielectric.))
The combination of Wang and Chang discloses that that the first dielectric material being made of a low-k dielectric material (materials that by necessity have a dielectric constant lower than 3.9) has lower dielectric constant than the high-k dielectric material (materials that by necessity have dielectric constant higher than 3.9.) of the second material.
Regarding claim 4, Wang as modified by Chang disclose the elements of claim 3.
Wang further discloses:
wherein the first dielectric constant is 3.9 or lower. (([0054], second dielectric layer 340 is a low-k dielectric material. Low-k dielectrics by necessity must have a dielectric constant lower than 3.9.)
Regarding claim 5, Wang as modified by Chang disclose the elements of claim 4.
Wang further discloses
wherein the first material is air. (Fig. 19, There is no material in the opening 390 until the conductive via, therefore the first material is air.)
Regarding claim 6, Wang as modified by Chang disclose the elements of claim 1.
Wang further discloses:
further comprising a non-conductive material (Wang, Fig. 20, first etch stop layer 360) in the second layer between respective walls of the second interlayer dielectric material (third dielectric material 380) and respective walls of the one or more conductive vias. (conductive via (400).)
Regarding claim 7, Wang discloses:
A system, comprising:
a substrate; (Wang, Fig. 20, wafer 310)
a power supply; and (Wang, [0012], as there is a power distribution system, as part of the power distribution system there must by necessity be a power supply.)
an integrated circuit (IC) die attached to the substrate and coupled to the power supply, (Wang, Fig. 20, [0052] the semiconductor is on the wafer 310.) the IC die comprising:
a first layer (Fig. 20, layer including dielectric material 320, conductive feature 330, and bonding layer 170.) with one or more conductive structures (conductive feature 330) in a first interlayer dielectric material, (dielectric material 320).)
with at least a portion of the one or more conductive structures at a first surface of the first layer; (See Fig. 20.)
a self-alignment layer in contact with non-conductive regions at the first surface of the first layer; (Fig. 19 and Fig. 20, second dielectric layer 340, first etch stop layer 360 and opening 390, where second dielectric layer 340 in contact with dielectric materials 320.)
a second layer with second interlayer dielectric material in contact with the self-alignment layer and the portion of the one or more conductive structures at the first surface of the first layer; and (See Fig. 20, third dielectric layer 380 in contact with the second dielectric layer 340 and portion 372 is in contact with conductive feature 330. The third dielectric layer 380 is also in indirect contact with contact feature 332.)
one or more conductive vias through the self-alignment layer and the second layer in respective contact with the portion of the one or more conductive structures at the first surface of the first layer, (See Fig. 10, conductive via 400.)
wherein the self-alignment layer comprises a first material where the self-alignment layer is in contact with the one or more conductive vias (Fig. 20, second dielectric layer 340 is in contact with conductive via 400.) and …
Wang does disclose a second material in the self-alignment layer such as etch stop layer 360 which is made from a high-k dielectric material ([0060]). While, the etch stop layer 360 does not contact conductive via 330, it does contact conductive via 332. Therefore, Wang does not appear to disclose where the second material of the self-alignment layer “is not in contact with the one or more conductive vias.”
Chang, which teaches a method of self-alignment of two more layers (Chang, Abstract), discloses having a spacers 114 which are in the self-alignment layer (Embodiment 1 shown in Figs. 1A- 1N, specifically Fig. 1C, layer which includes ILD 116 and the alignment structure 112 and spacers 114.) The spacer 114 is made of the same material as spacers 108. ([0024]) The spacer is made of silicon oxynitride (SiON, [0021]) which is a known high-k dielectric. (Wang discloses silicon oxynitride as high-k dielectric. Wang, [0021].) This is made of different material the ILD 116 layer which is made of low-k dielectric. (Chang, [0023]) Therefore the device made by the combination of Wang and Chang would have resulted in a device with predictable characteristics as described by the claimed invention. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang to have second material of the self-alignment layer is not in contact with the one or more conductive vias as taught by Chang for purposes of The ILD layer is able to be kept clean and fee of residue from other alignment structures that are formed in the ILD layer. (Chang, [0039].)
Regarding claim 8, Wang as modified by Chang disclose the elements of claim 7.
Wang further discloses:
wherein the first material of the self-alignment layer comprises a low-k material ([0054], second dielectric layer 340 is a low-k dielectric material. Therefore would have a dielectric constant lower than 3.9.)
Chang further discloses:
the second material of the self-alignment layer comprises a high- k material. (The spacer 114 is made of the same material as spacers 108. ([0024]) The spacer is made of silicon oxynitride which is a known high-k dielectric. (Wang discloses silicon oxynitride as high-k dielectric.) Therefore would have a dielectric constant higher than 3.9.)
Regarding claim 9, Wang as modified by Chang disclose the elements of claim 7.
Wang further discloses:
wherein a first dielectric constant of the first material of the self-alignment layer ([0054], second dielectric layer 340 is a low-k dielectric material.)
Chang further discloses:
a second dielectric constant of the second material of the self-alignment layer. (The spacer 114 is made of the same material as spacers 108. ([0024]) The spacer is made of silicon oxynitride which is a known high-k dielectric. (Wang discloses silicon oxynitride as high-k dielectric.))
The combination of Wang and Chang discloses that that the first dielectric material being made of a low-k dielectric material (materials that by necessity have a dielectric constant lower than 3.9) has lower dielectric constant than the high-k dielectric material (materials that by necessity have dielectric constant higher than 3.9.) of the second material.
Regarding claim 10, Wang as modified by Chang disclose the elements of claim 9.
Wang further discloses:
wherein the first dielectric constant is 3.9 or lower. (([0054], second dielectric layer 340 is a low-k dielectric material. Low-k dielectrics by necessity must have a dielectric constant lower than 3.9.)
Regarding claim 11, Wang as modified by Chang disclose the elements of claim 10.
Wang further discloses
wherein the first material is air. (Fig. 19, There is no material in the opening 390 until the conductive via, therefore the first material is air.)
Regarding claim 12, Wang as modified by Chang disclose the elements of claim 7.
Wang further discloses:
further comprising a non-conductive material (Wang, Fig. 20, first etch stop layer 360) in the second layer between respective walls of the second interlayer dielectric material (third dielectric material 380) and respective walls of the one or more conductive vias. (conductive via (400).)
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Wang as modified by Chang as applied to claims 4 and 10 above, and further in view of Yang US 20200124985 A1 (hereinafter Yang).
Regarding claim 5, Wang as modified by Chang disclose the elements of claim 4.
While Wang is considered to disclose that the first material is air. In the alternative, Yang, which teaches interconnect formation process (Yang, Abstract), discloses:
wherein the first material is air. (Yang, Fig. 10, void 1010 being an “air-gap” in side the dielectric liner layer 1000.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang as modified by Chang to have wherein the first material is air as taught by Yang for purposes of lowering the dielectric constant of the dielectric liner material. (Yang, [0040].)
Regarding claim 11, Wang as modified by Chang disclose the elements of claim 10.
While Wang is considered to disclose that the first material is air. In the alternative, Yang, which teaches interconnect formation process (Yang, Abstract), discloses:
wherein the first material is air. (Yang, Fig. 10, void 1010 being an “air-gap” inside the dielectric liner layer 1000.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang as modified by Chang to have wherein the first material is air as taught by Yang for purposes of lowering the dielectric constant of the dielectric liner material. (Yang, [0040].)
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kantarovsky US 20220223694 A1 – Process Figs. 15A which has low-k material 105 and a second material 113 that acts as a protective plug for via for self-aligned material.
Nakamura US 20150108604 A1 – Fig. 8, a semiconductor chip that is connected to a power supply IC.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812