Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated ####, claims ### are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed ### have been considered.
Claim Objections
Claims #### are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. [“Ternary content-addressable memory with MoS2 transistors for massively parallel data search”].
With respect to claim 1, Yang et al. disclose an integrated circuit (IC) die, comprising: a substrate [figs. 1a and 2a]; and an array of memory cells formed in or on the substrate [figs. 1c and 2a] and with a memory cell of the array of memory cells that includes a storage circuit that comprises a hysteretic-oxide material [“Circuit diagram of the simulated TCAM array, using the 2T2R MoS2-RRAM TCAM cells” – fig. 5a], wherein: the array of memory cells includes two or more hysteric-oxide memory cells coupled in parallel [fig. 5a]; and the array of memory cells is configured as a ternary content-addressable memory (TCAM) [2T2R MoS2-RRAM TCAM cells].
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. [“Ternary content-addressable memory with MoS2 transistors for massively parallel data search”].
With respect to claim 8, Yang et al. disclose a system, comprising: a substrate [figs. 1a and 2a]; a power supply [see Discussion on using MoS2 FETs for TCAMs section]; and an integrated circuit (IC) die attached to the substrate ["integrated into three-dimensional (3D) circuits" – 2nd par. of 2nd col. of 1st page (3D integration (e.g., monolithic 3D or stacking) commonly refers to building TCAM arrays directly on substrates over other circuitry.)] and coupled to the power supply, the IC die comprising: a first memory array; and a ternary content-addressable memory (TCAM) array associated with the first memory array [“the TCAM array can potentially be integrated into three-dimensional (3D) circuits with dense logic and memory layers” - 2nd par. of 2nd col. of 1st page (Stacking a TCAM on a first memory array represents dense, layered integration of distinct memory types.), wherein the TCAM array includes two or more hysteric-oxide memory cells [“the 2T2R TCAM cell, with two MoS2 FETs and two HfOx-based RRAMs” – figs. 1a and 5a].
With respect to claim 9, Yang et al. disclose at least two of the two or more hysteric-oxide memory cells are coupled in parallel. See fig. 5a.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. [“Ternary content-addressable memory with MoS2 transistors for massively parallel data search”].
With respect to claim 15, Yang et al. disclose a method, comprising: receiving a substrate [figs. 1a and 2a]; forming an array of memory cells in or on the substrate ["integrated into three-dimensional (3D) circuits" – 2nd par. of 2nd col. of 1st page (3D integration (e.g., monolithic 3D or stacking) commonly refers to building TCAM arrays directly on substrates over other circuitry.)] with a memory cell of the array of memory cells that includes a storage circuit that comprises a hysteretic-oxide material [“Circuit diagram of the simulated TCAM array, using the 2T2R MoS2-RRAM TCAM cells” – fig. 5a]; and configuring the array of memory cells as a ternary content-addressable memory (TCAM) [“the 2T2R TCAM cell, with two MoS2 FETs and two HfOx-based RRAMs” – figs. 1a and 5a].
Allowable Subject Matter
Claims 5-7 are allowable over the prior art of record.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 4: The IC die of claim 1, further comprising: a front-side memory formed in or on a front-side of the substrate, wherein the TCAM is associated with the front-side memory and wherein the TCAM is formed in or on a back-side of the substrate.
-with respect to claim 5, a first ferroelectric field effect transistor (FeFET); and a second FeFET, wherein a source terminal of the first FeFET is coupled to a source terminal of the second FeFET, a drain terminal of the first FeFET is coupled to a drain terminal of the second FeFET, and respective gates of the first and second FeFETs include the hysteretic- oxide material.
-with respect to claim 10: The system of claim 8, wherein the first memory array is formed in front-side metallization layers of the IC die, and wherein the TCAM array is formed in back-side metallization layers of the IC die.
-with respect to claim 11: The system of claim 8, wherein at least one of the two or more hysteric-oxide memory cells each further comprises: a first ferroelectric field effect transistor (FeFET); and a second FeFET, wherein a source terminal of the first FeFET is coupled to a source terminal of the second FeFET, a drain terminal of the first FeFET is coupled to a drain terminal of the second FeFET, and respective gates of the first and second FeFETs include hysteretic- oxide material.
-with respect to claim 14: The system of claim 8, further comprising: a cooler structure thermally coupled to the IC die and operable to remove heat from the IC die to achieve an operating temperature at or below -25°C.
-with respect to claim 17: The method of claim 15, further comprising: forming the TCAM in back-side metallization layers.
-with respect to claim 18: The method of claim 15, further comprising: forming a memory cell of the TCAM with a first ferroelectric field effect transistor (FeFET); and forming the memory cell of the TCAM with a second FeFET, wherein a source terminal of the first FeFET is coupled to a source terminal of the second FeFET, a drain terminal of the first FeFET is coupled to a drain terminal of the second FeFET, and respective gates of the first and second FeFETs include the hysteretic-oxide material.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 March 19, 2026
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