DETAILED ACTION
This action is responsive to the application No. 17/955,203 filed on September 28, 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 01/29/2026 responding to the Office action mailed on 11/04/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-8, 12-16, and newly added claims 21-27.
Claim Objections
Claims 1 and 21 are objected to because of the following informalities: claims 1 and 21 recite, “the front-side metallization layers comprising a first back-side metallization layer and one or more additional back-side metallization layers”. It appears that the Applicants intended for the claims to read “the back-side metallization layers comprising a first back-side metallization layer and one or more additional back-side metallization layers”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 4, 6, and 9-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi (US 2020/0135844).
Regarding Claim 1, Takahashi (see, e.g., Fig. 3 and annotated Fig. 3), teaches an apparatus, comprising:
a plurality of front-side metallization layers 110f of a monolithic integrated circuit (IC) die 300, the front-side metallization layers 110f comprising a first front-side metallization layer 1101f and one or more additional front-side metallization layers 110f (see, e.g., pars. 0020, 0032);
a plurality of back-side metallization layers 110bk of the monolithic IC die 300 opposite the front-side metallization layers 110f from transistors 106 of the monolithic IC die 300, the front-side metallization layers 110f comprising a first back-side metallization layer 1101bk and one or more additional back-side metallization layers 110bk, wherein the first front-side metallization layer 1101f is proximate to the first back-side metallization layer 1101bk (see, e.g., par. 0020); and
a vertical metallization structure 112 through at least the first front-side metallization layer 1101f and the first back-side metallization layer 1101bk, wherein the vertical metallization structure 112 electrically connects a first metallization structure 1081 of the one of the one or more additional front-side metallization layers 110f to a second metallization structure 110 of the one of the one or more additional back-side metallization layers 110bk (see, e.g., par. 0020).
Regarding Claim 2, Takahashi teaches all aspects of claim 1. Takahashi (see, e.g., Fig. 3 and annotated Fig. 3), teaches that the vertical metallization structure 112 is a metal via (see, e.g., par. 0020), the apparatus further comprising:
a capacitor structure 114 through at least the first front-side metallization layer 1101f and the first back-side metallization layer 1101bk, wherein the capacitor structure 114 electrically connects a third metallization structure 108a of the one of the one or more additional front-side metallization layers 1101f to a fourth metallization structure 108b of the one of the one or more additional back-side metallization layers 110bk (see, e.g., pars. 0021-0022, 0032-0033).
Regarding Claim 3, Takahashi teaches all aspects of claim 2. Takahashi (see, e.g., Fig. 3 and annotated Fig. 3), teaches that the capacitor structure 114 comprises a substantially cylindrical metal-insulator-metal (MIM) capacitor structure (see, e.g., pars. 0021-0022, 0032-0033).
Regarding Claim 4, Takahashi teaches all aspects of claim 3. Takahashi (see, e.g., Figs. 3, 13A, and annotated Fig. 3), teaches that the first metallization structure 1081, the second metallization structure 110, the third metallization structure 108a, or the fourth metallization structure 108b is to be coupled to a power source (see, e.g., par. 0057).
Regarding Claim 6, Takahashi teaches all aspects of claim 1. Takahashi (see, e.g., Fig. 3 and annotated Fig. 3), teaches:
a substrate 102 (see, e.g., par. 0020); and
a power supply V1, wherein the monolithic IC die 300 is attached to the substrate 102 and coupled to the power supply V1 (see, e.g., pars. 0032, 0066).
Regarding Claim 9, Takahashi teaches all aspects of claim 8. Takahashi (see, e.g., Figs. 3, 13A, and annotated Fig. 3), teaches that one of the first metallization structure 108a and the second metallization structure 108b is to be coupled to a power source (see, e.g., par. 0057).
Regarding Claim 10, Takahashi teaches all aspects of claim 9. Takahashi (see, e.g., Figs. 3, 13A, and annotated Fig. 3), teaches that the cylindrical MIM capacitor structure is proximate to a component 1302 that has an expected surge in power demand (see, e.g., par. 0066).
Regarding Claim 11, Takahashi teaches all aspects of claim 8. Takahashi (see, e.g., Figs. 4A), teaches a plurality of cylindrical MIM capacitors C1/C2 through the first front-side metallization layer 1101f and the first back-side metallization layer 1101bk respectively proximate to a plurality of components 106 that have an expected surge in power demand.
Regarding Claim 12, Takahashi (see, e.g., Figs. 11, 16-25), teaches a method, comprising:
forming a plurality of front-side metallization layers 110f over a substrate 102 comprising transistors 106, the front-side metallization layers 110f comprising a first front-side metallization layer 1101f and one or more additional front-side metallization layers 110f (see, e.g., par. 0020);
forming a plurality of back-side metallization layers 110bk opposite the front-side metallization layers 110f from the transistors 106, the back-side metallization layers 110bk comprising a first back-side metallization layer 1101bk and one or more additional back-side metallization layers 110bk, wherein the first front-side metallization layer 1101f is proximate to the first back-side metallization layer 1101bk (see, e.g., par. 0020); and
forming a vertical metallization structure 1102b through at least the first front-side metallization layer 1101f and the first back-side metallization layer 1101bk, wherein the vertical metallization structure 1102b contacts a first metallization structure 802a of the one of the one or more additional front-side metallization layers 110f and a second metallization structure 108b of the one of the one or more additional back-side metallization layers 110bk (see, e.g., pars. 0054, 0061, 0064).
Regarding Claim 13, Takahashi teaches all aspects of claim 12. Takahashi (see, e.g., Figs. 11, 16-25), teaches that forming the vertical metallization structure 1102b comprises:
forming a hole 1804 in at least the first front-side metallization layer 1101f and the first back side metallization layer 1101bk; and
depositing metal in the hole 1804 (see, e.g., par. 0080).
Regarding Claim 14, Takahashi teaches all aspects of claim 13. Takahashi (see, e.g., Figs. 16-25), teaches that forming the hole 1804 comprises:
breakthrough etching 1802 the first front-side metallization layer 110f and the first back-side metallization layer 1101bk (see, e.g., par. 0077).
Regarding Claim 15, Takahashi teaches all aspects of claim 13. Takahashi (see, e.g., Figs. 16-25), teaches forming a capacitor structure 114 through at least the first front-side metallization layer 110f and the first back-side metallization layer 1101bk.
Regarding Claim 16, Takahashi teaches all aspects of claim 15. Takahashi (see, e.g., Figs. 11, 16-25), teaches that forming the capacitor structure 114 comprises:
breakthrough etching a second hole 1804 in the at least the first front-side metallization layer 1101f and the first back-side metallization layer 1101bk (see, e.g., Fig. 18, par. 0077);
depositing a metal liner 1902 in the second hole 1804 (see, e.g., Fig. 19, par. 0078);
depositing a dielectric liner 2002 on the metal liner 1902 (see, e.g., Fig. 20, par. 0079); and
depositing metal 2102 in the dielectric liner 2002 (see, e.g., Fig. 21, par. 0080).
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The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-23 and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kalnitsky (US 2022/0285480).
Regarding Claim 21, Kalnitsky (see, e.g., Fig. 6B and Annotated Fig. 6B), teaches an apparatus, comprising:
a plurality of front-side metallization layers 108f of a monolithic integrated circuit (IC) die 618, the front-side metallization layers 108f comprising a first front-side metallization layer 1081f and one or more additional front-side metallization layers 108f (see, e.g., pars. 0020, 0060);
a plurality of back-side metallization layers 108bk of the monolithic IC die 618 opposite the front-side metallization layers 108f from transistors 603/607 of the monolithic IC die 618, the front-side metallization layers 108f comprising a first back-side metallization layer 1081bk and one or more additional back-side metallization layers 108bk, wherein the first front-side metallization layer 1081f is proximate to the first back-side metallization layer 1081bk (see, e.g., pars. 0060, 0062); and
a vertical metal via 218/220 and a vertical capacitor structure 118 each through at least the first front-side metallization layer 1081f and the first back-side metallization layer 1081bk, wherein the vertical metal via 218/220 and the vertical capacitor structure 118 each contact metallization structures 104b1/104b2 of the one of the one or more additional front-side metallization layers 108f and metallization structures 314/318 of the one of the one or more additional back-side metallization layers 108bk (see, e.g., pars. 0020, 0031, 0039).
Regarding Claim 22, Kalnitsky teaches all aspects of claim 21. Kalnitsky (see, e.g., Fig. 6B and Annotated Fig. 6B), teaches that the vertical capacitor structure 118 comprises a substantially cylindrical metal-insulator-metal (MIM) capacitor structure (see, e.g., par. 0022).
Regarding Claim 23, Kalnitsky teaches all aspects of claim 21. Kalnitsky (see, e.g., Figs. 6A-6B and Annotated Fig. 6B), teaches that at least one of the metallization structures 104b1/104b2 of the one of the one or more additional front-side metallization layers 108f and the metallization structures 314/318 of the one of the one or more additional back-side metallization layers 108bk are coupled to a power source (see, e.g., par. 0057).
Regarding Claim 25, Kalnitsky teaches all aspects of claim 21. Kalnitsky (see, e.g., Fig. 6B and Annotated Fig. 6B), teaches:
a substrate 102 (see, e.g., par. 0020); and
a power supply, wherein the monolithic IC die 618 is attached to the substrate 102 and coupled to the power supply (see, e.g., pars. 0057-0058).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2020/0135844).
Regarding Claim 5, Takahashi teaches all aspects of claim 2. Takahashi (see, e.g., Figs. 3, 13A, and annotated Fig. 3), teaches that the capacitor structure 114 is proximate to a component 1302 that has an expected surge in power demand (see, e.g., par. 0066).
Takahashi does not teach that the capacitor is within 10 nm of the component.
However, this claim limitation is merely considered a change in the distance between the capacitor structure 114 and component 1302 in Takahashi’s device. The specific claimed distance, absent any criticality, is only considered to be an obvious modification of the distance between the capacitor structure 114 and component 1302 in Takahashi’s device, as the courts have held that changes in distance without any criticality, are within the level of skill in the art. According to the courts, a particular distance is nothing more than one among numerous distances that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the claimed distance, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed distance in Takahashi’s device.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed distance between the capacitor structure and component or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen distance or upon another variable recited in a claim, the applicant must show that the chosen distance is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kalnitsky (US 2022/0285480).
Regarding Claim 24, Kalnitsky teaches all aspects of claim 21. Kalnitsky (see, e.g., Fig. 6B and Annotated Fig. 6B), teaches that the vertical capacitor structure 118 is proximate to a component 607 that has an expected surge in power demand (see, e.g., par. 0062).
Kalnitsky does not teach that the capacitor is within 10 nm of the component.
However, this claim limitation is merely considered a change in the distance between the capacitor structure 118 and component 607 in Kalnitsky’s device. The specific claimed distance, absent any criticality, is only considered to be an obvious modification of the distance between the capacitor structure 118 and component 607 in Kalnitsky’s device, as the courts have held that changes in distance without any criticality, are within the level of skill in the art. According to the courts, a particular distance is nothing more than one among numerous distances that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
See also the comments stated above in claim 5 regarding criticality which are considered repeated here.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2020/0135844) in view of McClean (WO-2018045052).
Regarding Claim 7, Takahashi teaches all aspects of claim 1. Takahashi does not teach a cooling structure operable to cool the monolithic IC die to a temperature below 0°C.
McClean, on the other hand, teaches a cooling structure operable to cool the monolithic IC die to a temperature below 0°C, to increase clock speed and increase CPU reliability (see, e.g., par. 0045).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Takahashi’s device, a cooling structure operable to cool the monolithic IC die to a temperature below 0°C, as taught by McClean, to increase clock speed and increase CPU reliability.
Regarding Claim 8, Takahashi and McClean teach all aspects of claim 7. McClean (see, e.g., Fig. 13), teaches that the cooling structure comprises microchannels laterally adjacent to a third metallization structure of the one of the one or more additional front-side metallization layers, the microchannels to convey a heat transfer fluid therein (see, e.g., pars. 0026, 0028, 0031, 0042).
Claims 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Kalnitsky (US 2022/0285480) in view of McClean (WO-2018045052).
Regarding Claim 26, Kalnitsky teaches all aspects of claim 21. Kalnitsky does not teach a cooling structure operable to cool the monolithic IC die to a temperature below 0°C.
McClean, on the other hand, teaches a cooling structure operable to cool the monolithic IC die to a temperature below 0°C, to increase clock speed and increase CPU reliability (see, e.g., par. 0045).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kalnitsky’s device, a cooling structure operable to cool the monolithic IC die to a temperature below 0°C, as taught by McClean, to increase clock speed and increase CPU reliability.
Regarding Claim 27, Kalnitsky and McClean teach all aspects of claim 26. McClean teaches that the cooling structure comprises microchannels laterally adjacent to metallization structures of the one of the one or more additional front-side metallization layers, the microchannels to convey a heat transfer fluid therein (see, e.g., pars. 0026, 0028, 0031, 0042).
Response to Arguments
Applicant’s arguments filed on 01/29/2026 with respect to the rejection of claims 1 and 12 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/
Primary Examiner, Art Unit 2814