DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11 and 17-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Manipatruni et al. (US 20220278116 A1, hereinafter Manipatruni).
With regards to claim 1, Manipatruni discloses an integrated circuit (IC) die, comprising a plurality of ferroelectric tunnel junction (FTJ) devices, (tunnel FET of FIGS. 1A-3B, see Paragraph [0080]) wherein at least one FTJ of the plurality of FTJ devices comprises:
first electrode; (bottom electrode BE1/2)
a second electrode; (top electrode TE2)
ferroelectric material (ferroelectric FE) disposed between the first and second electrodes; and
interface material (top electrode TE1) disposed between at least one of the first and second electrodes and the ferroelectric material. (See FIG. 3B)
With regards to claim 2, Manipatruni discloses the IC die of claim 1, wherein the interface material is formed in a vertical orientation that spans two or more layers of the IC die. (see FIG. 3B, showing the layer TE2 spanning at least layers ESL2 and 173)
With regards to claim 3, Manipatruni discloses the IC die of claim 1, wherein the interface material is formed in a horizontal orientation on a single layer of the IC die. (See FIG. 3B, showing the horizontal orientation on a single layer)
With regards to claim 4, Manipatruni discloses the IC die of claim 1, further comprising a memory circuit that includes the at least one FTJ device. (tunnel FET of FIGS. 1-3B, see Paragraph [0080])
With regards to claim 5, Manipatruni discloses the IC die of claim 1, further comprising a diode that includes the at least one FTJ device. (See FIG. 3B, wherein the transistor MN1/MN2 with the tunneling FET act as a diode)
With regards to claim 6, Manipatruni discloses the IC die of claim 1,further comprising:
block material (hafnium oxide of layer 172) disposed between at least one of the first and second electrodes and the ferroelectric material. (See paragraphs [0051]-[0053], showing the FE layer can be made of a layer of PZT and a layer of HfO)
With regards to claim 7, Manipatruni discloses the IC die of claim 6, further comprising a metal-insulator-metal (MIM) capacitor that includes the at least one FTJ device. (see FIG. 3B, showing the metal insulator metal capacitor 320)
With regards to claim 8, Manipatruni discloses a system, (tunnel FET system of FIGS. 1A-3B and 4, see Paragraph [0080]) comprising:
a substrate; (substrate 301)
a power supply; (power management 408, see FIG. 4) and
an integrated circuit (IC) die (die shown in FIG. 3B) attached to the substrate and coupled to the power supply, the IC die comprising a plurality of ferroelectric tunnel junction (FTJ) devices, wherein at least one FTJ of the plurality of FTJ devices comprises:
first electrode; (bottom electrode BE1/2)
a second electrode; (top electrode TE2)
ferroelectric material (ferroelectric FE 172) disposed between the first and second electrodes; and
interface material (top electrode TE1) disposed between at least one of the first and second electrodes and the ferroelectric material. (See FIG. 3B)
With regards to claim 9, Manipatruni discloses the system of claim 8, further comprising one or more of a diode and a memory circuit that includes the at least one FTJ device. (See FIG. 3B, wherein the transistor MN1/MN2 with the tunneling FET act as a diode with a memory circuit)
With regards to claim 10, Manipatruni discloses the system of claim 8, wherein the at least one FTJ device further comprises:
block material (hafnium oxide of layer 172) disposed between at least one of the first and second electrodes and the ferroelectric material. (See paragraphs [0051]-[0053], showing the FE layer 172 can be made of a layer of PZT and a layer of HfO)
With regards to claim 11, Manipatruni discloses the system of claim 10, further comprising a metal-insulator-metal (MIM) capacitor that includes the at least one FTJ device. (see FIG. 3B, showing the metal insulator metal capacitor 320)
With regards to claim 17, Manipatruni discloses a method, (tunnel FET of FIGS. 1A-3B and 4, see Paragraph [0080]) comprising:
receiving a substrate; (substrate 301)
forming a first metallization layer over the substrate that includes a first electrode (bottom electrode BE1/2) of a ferroelectric tunnel junction (FTJ) device; (see FIG. 3B)
forming a first dielectric layer (ferroelectric FE 172) over the first metallization layer, wherein the first dielectric layer includes a ferroelectric material of the FTJ device on the first electrode;
forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer includes an interface material (top electrode TE1) of the FTJ device on the ferroelectric material; and
forming a second metallization layer over the second dielectric layer, wherein the second metallization layer includes a second electrode of the FTJ device on the interface material.
With regards to claim 18, Manipatruni discloses the method of claim 17, further comprising:
forming a memory circuit that includes the FTJ device. (memory circuit shown in FIG. 3B)
With regards to claim 19, Manipatruni discloses the method of claim 17, further comprising:
forming a diode that includes the FTJ device. (See FIG. 3B, wherein the transistor MN1/MN2 with the tunneling FET act as a diode)
With regards to claim 20, Manipatruni discloses the method of claim 17, further comprising:
forming a third dielectric layer(hafnium oxide of layer 172) over one of the first metallization layer, the first dielectric layer, and the second dielectric layer,
wherein the third dielectric layer includes a blocking material of the FTJ device. (See paragraphs [0051]-[0053], showing the FE layer 172 can be made of a layer of PZT and a layer of HfO)
With regards to claim 21, Manipatruni discloses the method of claim 20, further comprising:
forming a metal-insulator-metal (MIM) capacitor that includes the FTJ device. (see FIG. 3B, showing the metal insulator metal capacitor 320)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-16 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manipatruni et al. (US 20220278116 A1, hereinafter Manipatruni) in view of Sharma et al (US 20240008286 A1, hereinafter Sharma)
With regards to claim 12, Manipatruni discloses the system of claim 8.
However, Manipatruni does not explicitly teach further comprising: a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below -25"C.
Sharma teaches a cooling structure (cooling system 700 with microchannels 677 shown in FIGS. 6-7) operable to remove heat from the IC die to achieve an operating temperature at or below -25"C. (Paragraphs [0102]-[0103]: “package-level active-cooling structures operable to remove heat from IC die 602 to achieve a very low operating temperature of IC die 602. As used herein, the term “very low operating temperature” indicates a temperature at or below 0° C., although even lower temperatures such as … an operating temperature at or below −196° C. (e.g., 77K) may be used. …FIG. 7 illustrates a view of an example two-phase immersion cooling system for low-temperature operation of an IC system, in accordance with some embodiments.”)
It would have been obvious to one of ordinary skill in the art to modify the device of Manipatruni to have the cooling structure of Sharma, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that the cooling system of Sharma allows for an improved performance, such as improved mobility and reduced leakage (see Sharma Paragraph [0032])
With regards to claim 13, Manipatruni in view of Sharma teaches the system of claim 12.
Sharma further teaches wherein the IC die comprises a plurality of metallization layers over a front side of the plurality of FTJ devices, the metallization layers (metallization layer 604 of) to provide signal routing for the plurality of FTJ devices, and wherein the cooling structure is over the plurality of metallization layers. (see FIG. 7)
With regards to claim 14, Manipatruni in view of Sharma teaches the system of claim 13.
Sharma further teaches wherein the cooling structure comprises a plurality of microchannels (microchannels 677) in the IC die and over the plurality of metallization layers, the microchannels to convey a heat transfer fluid therein. (liquid nitrogen, see Paragraph [0095])
With regards to claim 15, Manipatruni in view of Sharma teaches the system of claim 12.
Sharma further teaches wherein the cooling structure further comprises a chiller (chiller having package level microchannels 689) mounted to the IC die over the microchannels, the chiller comprising one of a solid body comprising second microchannels (microchannels 689) to convey a second heat transfer fluid therein or a heat sink for immersion in a low-boiling point liquid.
With regards to claim 16, Manipatruni in view of Sharma teaches the system of claim 12.
Sharma further teaches wherein the cooling structure is to convey liquid nitrogen (liquid nitrogen, see Paragraph [0095]) to achieve an operating temperature at or below about -196°C. (Paragraphs [0102]-[0103]: “package-level active-cooling structures operable to remove heat from IC die 602 to achieve a very low operating temperature of IC die 602. As used herein, the term “very low operating temperature” indicates a temperature at or below 0° C., although even lower temperatures such as … an operating temperature at or below −196° C. (e.g., 77K) may be used. …FIG. 7 illustrates a view of an example two-phase immersion cooling system for low-temperature operation of an IC system, in accordance with some embodiments.”)
With regards to claim 22, Manipatruni discloses the system of claim 17.
However, Manipatruni does not explicitly teach further comprising:
forming a cooling structure over the first and second metallization layers, wherein the cooling structure is operable to remove heat from the FTJ device to achieve an operating temperature at or below -25°C.
Sharma teaches a cooling structure (cooling system 700 with microchannels 677 shown in FIGS. 6-7) operable to remove heat from the IC die to achieve an operating temperature at or below -25"C. (Paragraphs [0102]-[0103]: “package-level active-cooling structures operable to remove heat from IC die 602 to achieve a very low operating temperature of IC die 602. As used herein, the term “very low operating temperature” indicates a temperature at or below 0° C., although even lower temperatures such as … an operating temperature at or below −196° C. (e.g., 77K) may be used. …FIG. 7 illustrates a view of an example two-phase immersion cooling system for low-temperature operation of an IC system, in accordance with some embodiments.”)
It would have been obvious to one of ordinary skill in the art to modify the device of Manipatruni to have the cooling structure of Sharma, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that the cooling system of Sharma allows for an improved performance, such as improved mobility and reduced leakage (see Sharma Paragraph [0032])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Thareja et al. (US 20210202507 A1) – ferroelectric capacitor
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812