DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1, 3, 12, 14 and 21-22 in the Applicant’s response dated 4 June 2026. The claim amendments have been addressed below.
The Examiner acknowledges the addition of new claims 23-28 in the Applicant’s response dated 4 June 2026. The new claims have been addressed below.
The Examiner acknowledges the cancellation of claims 2, 4-11, 13 and 15-20 in the Applicant’s response dated 4 June 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo-Chi Tu et al. (US 2019/0244895 A1; hereinafter “Tu”) in view of Richard C. Blish, II (US 2008/0298017 A1; hereinafter “Blish”).
Regarding Claim 1, Tu teaches an integrated circuit (IC) die (700, Fig. 7, para [0045] describes an integrated chip 700), comprising:
a plurality of metallization layers (714 and 704, Fig. 7, para [0047] describes via layers 714 and metal wire layers 704 comprising a plurality of metallization layers); and
transistors and metal-insulator-metal (MIM) decoupling capacitors interconnected through the metallization layers (716, 706a and 706b, Fig. 7, para [0051] describes transistors 716 interconnected to MIM decoupling capacitors 706a and 706b through the metallization layers as the MIM decoupling capacitors 706a and 706b may be interconnected to the transistors through at least upper wire layer 704d and 704c), each of the MIM decoupling capacitors within the metallization layers (706a and 706b, Fig. 7 depicts wherein the MIM decoupling capacitors 706a and 706b are located in a decoupling region 701a of the metallization layers), and comprising:
a first electrode (708, Fig. 7, para [0047] describes wherein the MIM decoupling capacitors comprise a lower electrode 708),
a second electrode (712, Fig. 7, para [0047] describes wherein the MIM decoupling capacitors comprise an upper electrode 712), and
inorganic solid electrolyte material between the first electrode and the second electrode (710 and 310, Fig. 3 and Fig. 7, para [0047] describes a capacitor dielectric 710 between the first electrode 708 and second electrode 712 wherein para [0026] further describes wherein a capacitor dielectric layer 310 for a MIM capacitor of various embodiments such as found in Fig. 7 may comprise an inorganic solid electrolyte material such as nickel oxide);
Tu fails to explicitly disclose a plurality of microchannels over a plurality of metallization layers, the microchannels to convey a heat transfer fluid therein; and wherein the heat transfer fluid is to remove heat from the IC die and achieve an operating temperature at or below -25°C.
However, Blish teaches a similar integrated circuit (IC) die further comprising a plurality of microchannels (330, Fig. 5A, para [0044] describes channels 330 of a cooling structure formed in a semiconductor base 332 wherein para [0043] describes the base 332 as part of an IC) over a plurality of metallization layers (336, Fig. 5A, para [0044] describes vias 336 through which the channels are coupled wherein the microchannels 330 are over the lower metallization layers 336), the microchannels to convey a heat transfer fluid therein (330, Fig. 5A, para [0048] describes wherein the microchannels 330 convey coolant through the semiconductor device); and
wherein the heat transfer fluid is to remove heat from the IC die and achieve an operating temperature at or below -25°C (330, Fig. 5A, para [0005] describes wherein a known technique for cooling involves supplying a liquid such as liquid nitrogen wherein the embodiment of Blish conveys a liquid coolant that may be liquid nitrogen as a heat transfer fluid supplied through microchannels 330 to remove heat from the IC die and further wherein para [0057] describes the integrated circuit of Blish may be used at cryogenic temperatures wherein cryogenic temperatures and temperatures of liquid nitrogen are known to be at or below a temperature of -196°C resulting in the heat transfer fluid being used to remove heat from the IC die and achieve an operating temperate that is at or below -25°C).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tu with Blish to further disclose an integrated circuit die which comprises a plurality of microchannels over a plurality of metallization layers, the microchannels to convey a heat transfer fluid therein and wherein the heat transfer fluid is to remove heat from the IC die and achieve an operating temperature at or below -25°C in order to provide the advantage of providing better heat management for the integrated circuit device through the controlled use of microchannels (Blish, para [0047]).
Regarding Claim 3, the combination of Tu and Blish teaches the IC die of claim 1, wherein the inorganic solid electrolyte material comprises one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride (Tu, 710 and 310, Fig. 3 and Fig. 7, para [0047] and para [0026] describes wherein a capacitor dielectric layer 310 for a MIM capacitor of various embodiments such as the capacitor dielectric layer 710 from Fig. 7 may comprise an inorganic solid electrolyte material such as nickel oxide).
Regarding Claim 25, the combination of Tu and Blish teaches the IC die of claim 1, wherein the operating temperature is at or below -50°C (Blish, para [0057] describes wherein the integrated circuit of Blish may be used at cryogenic temperatures wherein cryogenic temperatures and temperatures of liquid nitrogen are known to be at or below a temperature of -196°C resulting in the heat transfer fluid being used to remove heat from the IC die and achieve an operating temperate that is at or below -50°C).
Regarding Claim 26, the combination of Tu and Blish teaches the IC die of claim 1, wherein the operating temperature of the IC die is maintained at or below -70°C (Blish, para [0057] describes wherein the integrated circuit of Blish may be used at cryogenic temperatures wherein cryogenic temperatures and temperatures of liquid nitrogen are known to be at or below a temperature of -196°C resulting in the heat transfer fluid being used to remove heat from the IC die and achieve an operating temperate that is at or below -70°C).
Claims 12, 14, 21-22 and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo-Chi Tu et al. (US 2019/0244895 A1; hereinafter “Tu”) in view of Yu-Xuan Huang et al. (US 2021/0358842 A1; hereinafter “Huang”) and in further view of Richard C. Blish, II (US 2008/0298017 A1; hereinafter “Blish”).
Regarding Claim 12, Tu teaches a system, comprising:
a substrate (102, Fig. 7, para [0016] describes a substrate 102);
a power supply (VDD, Fig. 7, para [0047] describes a power supply voltage VDD provided by a power rail configured to provide power supply voltage from a power supply); and an integrated circuit (IC) die attached to the substrate and coupled to the power supply (700 and VDD, Fig. 7, para [0046] describes an integrated chip 700 attached to the substrate 102 and coupled to the power supply rail supplying a power supply voltage VDD and connected to the power supply), the IC die comprising;
transistors (716, Fig. 7, para [0051] describes transistors 716);
back-side metallization layers (714 and 704, Fig. 7, para [0047] describes via layers 714 and metal wire layers 704 comprising a plurality of metallization layers wherein para [0016] describes the metallization layers as a back-end-of-the-line metallization stack);
a plurality of metal-insulator-metal (MIM) decoupling capacitors within the back-side metallization layers (706a and 706b, Fig. 7, para [0047] describes a plurality of MIM decoupling capacitors 706a and 706b wherein the MIM decoupling capacitors 706a and 706b are located in a decoupling region 701a of the backside metallization layers), each of the capacitors comprising:
a first electrode (708, Fig. 7, para [0047] describes wherein the MIM decoupling capacitors comprise a lower electrode 708),
a second electrode (712, Fig. 7, para [0047] describes wherein the MIM decoupling capacitors comprise an upper electrode 712), and
inorganic solid-state electrolyte material disposed between the first electrode and the second electrode (710 and 310, Fig. 3 and Fig. 7, para [0047] describes a capacitor dielectric 710 between the first electrode 708 and second electrode 712 wherein para [0026] further describes wherein a capacitor dielectric layer 310 for a MIM capacitor of various embodiments such as found in Fig. 7 may comprise an inorganic solid electrolyte material such as nickel oxide);
Tu fails to explicitly disclose front-side metallization layers; and back-side metallization layers coupled to the front-side metallization layers.
However, Huang teaches a similar system further comprising front-side metallization layers (120, Fig. 28G, para [0066] describes a front-side interconnect structure 120); and
back-side metallization layers coupled to the front-side metallization layers (136, Fig. 28G, para [0066] describes a back-side metallization layers 136 including decoupling capacitors 142 coupled to the front-side metallization layers 120).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tu with Huang to further disclose a system comprising front-side metallization layers and back-side metallization layers coupled to the front-side metallization layers in order to provide the advantage of increasing a gate density of a nano-FET or interconnect density of a front-side interconnect structure by placing power rails on a backside of a system (Huang, para [0086]).
Tu and Huang fail to explicitly disclose a plurality of microchannels over the front-side metallization layers, the microchannels to convey a heat transfer fluid therein to remove heat from the IC die and achieve an operating temperature at or below -25°C.
However, Blish teaches a system further comprising a plurality of microchannels (330, Fig. 5A, para [0044] describes channels 330 of a cooling structure formed in a semiconductor base 332 wherein para [0043] describes the base 332 as part of an IC) over a plurality of metallization layers (336, Fig. 5A, para [0044] describes vias 336 through which the channels are coupled wherein the microchannels 330 are over the lower metallization layers 336), the microchannels to convey a heat transfer fluid therein (330, Fig. 5A, para [0048] describes wherein the microchannels 330 convey coolant through the semiconductor device); and
wherein the heat transfer fluid is to remove heat from the IC die and achieve an operating temperature at or below -25°C (330, Fig. 5A, para [0005] describes wherein a known technique for cooling involves supplying a liquid such as liquid nitrogen wherein the embodiment of Blish conveys a liquid coolant that may be liquid nitrogen as a heat transfer fluid supplied through microchannels 330 to remove heat from the IC die and further wherein para [0057] describes the integrated circuit of Blish may be used at cryogenic temperatures wherein cryogenic temperatures and temperatures of liquid nitrogen are known to be at or below a temperature of -196°C resulting in the heat transfer fluid being used to remove heat from the IC die and achieve an operating temperate that is at or below -25°C).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tu and Huang with Blish to further disclose a system which comprises a plurality of microchannels over a plurality of metallization layers, the microchannels to convey a heat transfer fluid therein and wherein the heat transfer fluid is to remove heat from the IC die and achieve an operating temperature at or below -25°C in order to provide the advantage of providing better heat management for the integrated circuit device through the controlled use of microchannels (Blish, para [0047]).
Regarding Claim 14, the combination of Tu, Huang and Blish teaches the system of claim 12, wherein the inorganic solid electrolyte material comprises one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride (Tu, 710 and 310, Fig. 3 and Fig. 7, para [0047] and para [0026] describes wherein a capacitor dielectric layer 310 for a MIM capacitor of various embodiments such as the capacitor dielectric layer 710 from Fig. 7 may comprise an inorganic solid electrolyte material such as nickel oxide).
Regarding Claim 21, the combination of Tu, Huang and Blish teaches the system of claim 12, further comprising a chiller mounted to the IC die over the microchannels (Blish, 112, Fig. 3B, para [0054] describes wherein a heat exchanger 112 which may be mounted over the IC die as shown in Fig. 3B, may be used to provide further cooling power in conjunction with the microchannels shown in Fig. 5A), the chiller comprising one of a solid body comprising second microchannels to convey a second heat transfer fluid therein (Blish, 112, Fig. 3B, para [0039] describes wherein the chiller 112 comprised further microchannels which may supply coolant to the IC device wherein chiller 112 is depicted as having a solid body portion) or a heat sink for immersion in a low-boiling point liquid.
Regarding Claim 22, the combination of Tu, Huang and Blish teaches the system of claim 12, wherein the heat transfer fluid is liquid nitrogen (Blish, para [0005] describes wherein a known technique for cooling involves supplying a liquid such as liquid nitrogen wherein the system of Blish conveys a liquid coolant that may be liquid nitrogen).
Regarding Claim 27, the combination of Tu, Huang and Blish teaches the system of claim 12, wherein the operating temperature is at or below -50°C (Blish, para [0057] describes wherein the integrated circuit of Blish may be used at cryogenic temperatures wherein cryogenic temperatures and temperatures of liquid nitrogen are known to be at or below a temperature of -196°C resulting in the heat transfer fluid being used to remove heat from the IC die and achieve an operating temperate that is at or below -50°C).
Regarding Claim 28, the combination of Tu, Huang and Blish teaches the system of claim 12, wherein the operating temperature of the IC die is maintained at or below -70°C (Blish, para [0057] describes wherein the integrated circuit of Blish may be used at cryogenic temperatures wherein cryogenic temperatures and temperatures of liquid nitrogen are known to be at or below a temperature of -196°C resulting in the heat transfer fluid being used to remove heat from the IC die and achieve an operating temperate that is at or below -70°C).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo-Chi Tu et al. (US 2019/0244895 A1; hereinafter “Tu”) in view of Richard C. Blish, II (US 2008/0298017 A1; hereinafter “Blish”) and in further view of Thomas L. Sounart et al. (US 2020/0051743 A1; hereinafter “Sounart”).
Regarding Claim 23, the combination of Tu and Blish disclose all the limitations of claim 1.
Tu and Blish fail to explicitly disclose the IC die of claim 1, wherein each of the MIM decoupling capacitors has a charge density greater than 5000 nF/mm2.
However, Sounart teaches a similar IC die, wherein each of the MIM decoupling capacitors has a charge density greater than 5000 nF/mm2 (210, Fig. 2, para [0026] describes a MIM capacitor 210 with a capacitance density in a range of 10-10,000 nF/mm2 wherein a capacitance density in of 10,000 nF/mm2 is greater than 5000 nF/mm2 and further wherein the MIM capacitor 210 is a similar backside metallization layer MIM capacitor used in power devices as disclosed by Tu and the instant application).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tu and Huang with Sounart to further disclose an IC die wherein each of the MIM decoupling capacitors has a charge density greater than 5000 nF/mm2 in order to provide the advantage of enabling a capacitor dielectric and adjacent seed layers with high permittivity to produce a capacitor with a correspondingly high capacitance density reducing the size of capacitor needed in high power devices therefore increasing manufacturing yield (Sounart, para [0002] and para [0026]) and to further provide the well-known advantage of providing a capacitor structure which may be utilized in power delivery requiring large capacitances therefore increasing device versatility.
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo-Chi Tu et al. (US 2019/0244895 A1; hereinafter “Tu”) in view of Yu-Xuan Huang et al. (US 2021/0358842 A1; hereinafter “Huang”) and in view of Richard C. Blish, II (US 2008/0298017 A1; hereinafter “Blish”) and in further view of Thomas L. Sounart et al. (US 2020/0051743 A1; hereinafter “Sounart”).
Regarding Claim 24, the combination of Tu, Huang and Blish disclose all the limitations of claim 12.
Tu, Huang and Blish fail to explicitly disclose the system of claim 12, wherein each of the MIM decoupling capacitors has a charge density greater than 5000 nF/mm2.
However, Sounart teaches a similar system, wherein each of the MIM decoupling capacitors has a charge density greater than 5000 nF/mm2 (210, Fig. 2, para [0026] describes a MIM capacitor 210 with a capacitance density in a range of 10-10,000 nF/mm2 wherein a capacitance density in of 10,000 nF/mm2 is greater than 5000 nF/mm2 and further wherein the MIM capacitor 210 is a similar backside metallization layer MIM capacitor used in power devices as disclosed by Tu and the instant application).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tu, Huang and Blish with Sounart to further disclose a system wherein each of the MIM decoupling capacitors has a charge density greater than 5000 nF/mm2 in order to provide the advantage of enabling a capacitor dielectric and adjacent seed layers with high permittivity to produce a capacitor with a correspondingly high capacitance density reducing the size of capacitor needed in high power devices therefore increasing manufacturing yield (Sounart, para [0002] and para [0026]) and to further provide the well-known advantage of providing a capacitor structure which may be utilized in power delivery requiring large capacitances therefore increasing device versatility.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3, 12, 14 and 21-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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