DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species B and Species II in the reply filed on 15 December 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kazuaki Kurihara et al. (US 2007/0141800 A1; hereinafter “Kurihara”).
Regarding Claim 1, Kurihara teaches an integrated circuit (IC) die, comprising:
front-side layers (FL, annotated Fig. 13B, para [0291] describes wherein a front side of the substrate 10 is where the protection film 30 and solder bumps 36 are formed as shown in annotated Fig. 13B by front-side layers FL);
back-side layers coupled to the front-side layers (BL, annotated Fig. 13B depicts back-side layers BL coupled to the front side layers FL) ; and
a capacitor in the back-side layers (20a, Fig. 13B, para [0202] describes a capacitor 20a which can be seen in the back-side layers BL of annotated Fig. 13B), the capacitor comprising:
a first electrode (14, Fig. 13B, para [0202] describes a capacitor electrode 14),
a second electrode (18, Fig. 13B, para [0202] describes a capacitor electrode 18), and
solid-state electrolyte material disposed between the first electrode and the second electrode (16, Fig. 13B, para [0202] describes a capacitor dielectric film 16 which can be seen between the first electrode 14 and second electrode 18 in Fig. 13B wherein para [0546] further describes wherein capacitor dielectric film 16 may be comprised of a niobium oxide such as the solid-state electrolyte material of the instant application).
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Regarding Claim 2, Kurihara teaches the IC die of claim 1, wherein the solid-state electrolyte material comprises an inorganic solid electrolyte material (16, para [0546] describes wherein dielectric film 16 comprises a solid-state electrolyte material such as niobium oxide further wherein it does not disclose dielectric film 16 may be comprised of a carbon-based organic material).
Regarding Claim 3, Kurihara teaches the IC die of claim 2, wherein the inorganic solid electrolyte material comprises one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride (16, Fig. 13B, para [0202] and para [0546] describes a capacitor dielectric film 16 wherein capacitor dielectric film 16 may be comprised of at least one layer of niobium oxide).
Regarding Claim 4, Kurihara teaches the IC die of claim 1, wherein the capacitor in the back-side layers comprises a decoupling capacitor (para [0287] describes wherein the capacitor parts 20a can help to more surely remove source voltage change and radio-frequency noises, effectively acting as a decoupling capacitor).
Regarding Claim 5, Kurihara teaches the IC die of claim 4, wherein the decoupling capacitor comprises a metal- insulator-metal (MIM) decoupling capacitor (para [0287] describes wherein the capacitor parts 20a can help to more surely remove source voltage change and radio-frequency noises, effectively acting as a decoupling capacitor and further wherein the composition of the capacitor 20a comprises a first electrode of a metal material such as platinum as described in para [0104], a second platinum electrode 18 as described in para [0106] and a dielectric film 16 therebetween resulting in a metal-insulator-metal decoupling capacitor).
Regarding Claim 6, Kurihara teaches the IC die of claim 1, wherein the capacitor in the back-side layers comprises a supercapacitor (para [0311] describes wherein the present embodiment enables a large capacitance per a unit area in the thin film capacitor 20a such as may be found in a supercapacitor).
Regarding Claim 7, Kurihara teaches an integrated circuit (IC) die, comprising a plurality of capacitor devices (PC, annotated Fig. 13B II depicts a plurality of capacitor devices PC), wherein at least one capacitor of the plurality of capacitor devices comprises:
a first electrode (14, Fig. 13B, para [0202] describes a capacitor electrode 14);
a second electrode (18, Fig. 13B, para [0202] describes a capacitor electrode 18); and
material disposed between the first electrode and the second electrode, wherein the material comprises one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride (16, Fig. 13B, para [0202] describes a capacitor dielectric film 16 which can be seen disposed between first electrode 14 and second electrode 18 in Fig. 143B and para [0546] wherein capacitor dielectric film 16 may be comprised of at least one layer of niobium oxide).
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Regarding Claim 8, Kurihara teaches the IC die of claim 7, further comprising:
front-side layers (FL, annotated Fig. 13B, para [0291] describes wherein a front side of the substrate 10 is where the protection film 30 and solder bumps 36 are formed as shown in annotated Fig. 13B by front-side layers FL); and
back-side layers coupled to the front-side layers (BL, annotated Fig. 13B depicts back-side layers BL coupled to the front side layers FL), wherein the at least one capacitor is in the back-side layers (20a, Fig. 13B, para [0202] describes a capacitor 20a which can be seen in the back-side layers BL of annotated Fig. 13B).
Regarding Claim 9, Kurihara teaches the IC die of claim 8, wherein the at least one capacitor formed in the back-side layers comprises a decoupling capacitor (para [0287] describes wherein the capacitor parts 20a can help to more surely remove source voltage change and radio-frequency noises, effectively acting as a decoupling capacitor).
Regarding Claim 10, Kurihara teaches the IC die of claim 9, wherein the decoupling capacitor comprises a metal- insulator-metal (MIM) decoupling capacitor (para [0287] describes wherein the capacitor parts 20a can help to more surely remove source voltage change and radio-frequency noises, effectively acting as a decoupling capacitor and further wherein the composition of the capacitor 20a comprises a first electrode of a metal material such as platinum as described in para [0104], a second platinum electrode 18 as described in para [0106] and a dielectric film 16 therebetween resulting in a metal-insulator-metal decoupling capacitor).
Regarding Claim 11, Kurihara teaches the IC die of claim 8, wherein the at least one capacitor in the back-side layers comprises a supercapacitor (para [0311] describes wherein the present embodiment enables a large capacitance per a unit area in the thin film capacitor 20a such as may be found in a supercapacitor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kazuaki Kurihara et al. (US 2007/0141800 A1; hereinafter “Kurihara”) in view of Sukhvinder Kang et al. (US 6,233,960 B1; hereinafter “Kang”).
Regarding Claim 12, Kurihara teaches a system, comprising:
a substrate (10, Fig. 12A and Fig. 13B, para [0170] describes a base substrate 10 as seen labeled in Fig. 12A and carried through to the final device of the same embodiment of Fig. 12A in Fig. 13B); and
an integrated circuit (IC) die attached to the substrate (ICD, Fig. 13B depicts an integrated circuit die ICD attached to substrate 10), the IC die comprising front-side layers (FL, annotated Fig. 13B, para [0291] describes wherein a front side of the substrate 10 is where the protection film 30 and solder bumps 36 are formed as shown in annotated Fig. 13B by front-side layers FL), back-side layers coupled to the front-side layers (BL, annotated Fig. 13B depicts back-side layers BL coupled to the front side layers FL), and a capacitor in the back-side layers (20a, Fig. 13B, para [0202] describes a capacitor 20a which can be seen in the back-side layers BL of annotated Fig. 13B), the capacitor comprising:
a first electrode (14, Fig. 13B, para [0202] describes a capacitor electrode 14),
a second electrode (18, Fig. 13B, para [0202] describes a capacitor electrode 18), and
solid-state electrolyte material disposed between the first electrode and the second electrode (16, Fig. 13B, para [0202] describes a capacitor dielectric film 16 which can be seen between the first electrode 14 and second electrode 18 in Fig. 13B wherein para [0546] further describes wherein capacitor dielectric film 16 may be comprised of a niobium oxide such as the solid-state electrolyte material of the instant application).
Kurihara fails to explicitly teach a power supply; and an integrated circuit (IC) die attached to the substrate and coupled to the power supply.
However, Kang teaches a similar system comprising:
a power supply (65, Fig. 4, column 4, lines 54-60 describe a power supply 65 powering a system including integrated chip modules); and
an integrated circuit (IC) die attached to the substrate and coupled to the power supply (76 and 14, Fig. 3 and Fig. 4, columns 4, lines 54-60 describe an integrated chip module which is powered by power supply 65 and housed in housing 76 wherein integrated chip module 14 of Fig. 3 is describes in column 4, lines 38-47 as comprising a substrate base 54 and capacitors 58 such as found in the disclosure of Kurihara).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kurihara with Kang to further disclose a system which comprises a power supply coupled to an integrated circuit in order to provide the well-known advantage of providing the integrated circuit with the load required for the integrated circuit die to function properly.
Regarding Claim 13, the combination of Kurihara and Kang disclose the system of claim 12, wherein the solid-state electrolyte material comprises an inorganic solid electrolyte material (Kurihara, 16, para [0546] describes wherein dielectric film 16 comprises a solid-state electrolyte material such as niobium oxide further wherein it does not disclose dielectric film 16 may be comprised of a carbon based material).
Regarding Claim 14, the combination of Kurihara and Kang disclose the system of claim 13, wherein the inorganic solid electrolyte material comprises one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride (Kurihara, 16, Fig. 13B, para [0202] and para [0546] describes a capacitor dielectric film 16 wherein capacitor dielectric film 16 may be comprised of at least one layer of niobium oxide).
Regarding Claim 15, the combination of Kurihara and Kang disclose the system of claim 12, wherein the capacitor in the back-side layers comprises a decoupling capacitor (Kurihara, para [0287] describes wherein the capacitor parts 20a can help to more surely remove source voltage change and radio-frequency noises, effectively acting as a decoupling capacitor).
Regarding Claim 16, the combination of Kurihara and Kang disclose the system of claim 15, wherein the decoupling capacitor comprises a metal- insulator-metal (MIM) decoupling capacitor (Kurihara, para [0287] describes wherein the capacitor parts 20a can help to more surely remove source voltage change and radio-frequency noises, effectively acting as a decoupling capacitor and further wherein the composition of the capacitor 20a comprises a first electrode of a metal material such as platinum as described in para [0104], a second platinum electrode 18 as described in para [0106] and a dielectric film 16 therebetween resulting in a metal-insulator-metal decoupling capacitor).
Regarding Claim 17, the combination of Kurihara and Kang disclose the system of claim 12, wherein the capacitor in the back-side layers comprises a supercapacitor (Kurihara, para [0311] describes wherein the present embodiment enables a large capacitance per a unit area in the thin film capacitor 20a such as may be found in a supercapacitor).
Regarding Claim 18, the combination of Kurihara and Kang disclose the system of claim 12, further comprising:
a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below -25°C (Kang, 10, Fig. 1 and Fig. 2, column 3, lines 47-50 describe a cooling assembly 10 of Fig. 1 which cools the IC module to temperatures in the range of -40°C to -60°C wherein the cooling system 10 of Fig. 1 is a same cooling system from which Fig. 2 and Fig. 3 are comprised wherein a difference is only present in a shape of a spot cooling evaporator 13).
Regarding Claim 19, the combination of Kurihara and Kang disclose the system of claim 18, wherein the IC die comprises a plurality of metallization layers over a front side of the plurality of capacitor devices (Kurihara, 34 and 36, Fig. 13B, para [0164] describes outside connection electrodes 34a and 34b connected to solder bumps 36 which form metallization layers over a front side FL of the plurality of capacitor devices 20a), the metallization layers to provide signal routing for the plurality of capacitor devices (para [0163] describes wherein outside connection electrodes 34a and 34b are formed for the connection to the outside therefore providing signal routing for the capacitor devices 20a), and wherein the cooling structure is over the plurality of metallization layers (Kang, 10, Fig. 1-Fig. 3 depicts wherein the cooling system 10 is above the integrated circuit module 14 wherein upon combining Kurihara with Kang the cooling system 10 of Kang would be over the plurality of metallization layers 34 and 36 of Kurihara).
Claims 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kazuaki Kurihara et al. (US 2007/0141800 A1; hereinafter “Kurihara”) in view of Sukhvinder Kang et al. (US 6,233,960 B1; hereinafter “Kang”) and in further view of Richard C. Blish, II (US 2008/0298017 A1; hereinafter “Blish II”).
Regarding Claim 20, the combination of Kurihara and Kang disclose the limitations of claim 19,
Kurihara and Kang fail to explicitly disclose the system of claim 19, wherein the cooling structure comprises a plurality of microchannels in the IC die and over the plurality of metallization layers, the microchannels to convey a heat transfer fluid therein.
However, Blish II teaches a similar system wherein the cooling structure comprises a plurality of microchannels in the IC die (330, Fig. 5A, para [0044] describes channels 330 of a cooling structure formed in a semiconductor base 332 wherein para [0043] describes the base 332 as part of an IC) and over the plurality of metallization layers (336, Fig. 5A, para [0044] describes vias 336 through which the channels are coupled and further wherein upon combining Kurihara and Kang with Blish II, the microchannels of Blish II would be over the metallization layers of Kurihara 34 and 36), the microchannels to convey a heat transfer fluid therein (para [0048] describes wherein the microchannels 330 convey coolant through the semiconductor device).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kurihara and Kang with Blish II to further disclose a system which comprises a microchannel structure for providing cooling within an IC die in order to provide the advantage of providing better heat management for the integrated circuit device through the controlled use of microchannel (Blish II, para [0047]).
Regarding Claim 21, the combination of Kurihara, Kang and Blish II disclose the system of claim 20, wherein the cooling structure further comprises a chiller mounted to the IC die over the microchannels (Blish II, 112, Fig. 3B, para [0054] describes wherein a heat exchanger 112 which may be mounted over the IC die as shown in Fig. 3B, may be used to provide further cooling power in conjunction with the microchannels shown in Fig. 5A), the chiller comprising one of a solid body comprising second microchannels to convey a second heat transfer fluid therein (Blish II, 112, Fig. 3B, para [0039] describes wherein the chiller 112 comprised further microchannels which may supply coolant to the IC device wherein chiller 112 is depicted as having a solid body portion) or a heat sink for immersion in a low-boiling point liquid.
Regarding Claim 22, the combination of Kurihara, Kang and Blish II disclose the wherein the cooling structure is to convey liquid nitrogen to achieve an operating temperature at or below about -196°C (Blish II, para [0005] describes wherein a known technique for cooling involves supplying a liquid such as liquid nitrogen wherein the embodiment of Blish II conveys a liquid coolant that may be liquid nitrogen wherein para [0057] describes the embodiment of Blish II may be used at cryogenic temperatures wherein cryogenic temperatures and temperatures of liquid nitrogen are known to be at or below a temperature of 196°C).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898