DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 in the reply filed on 18 May 2026 is acknowledged. Claims 17-20 stand as canceled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20110108992 (Chanda) and US 20210129261 (Mayberry).
As to claim 1: Chanda teaches an integrated circuit (IC) die, comprising:
a first conductive structure for a terminal of a capacitively coupled device (Chanda Fig 6, 63);
a second conductive structure aligned with the first conductive structure for a signal to be capacitively coupled to the terminal of the capacitively coupled device (right-most 33; these lines necessarily capacitively coupled);
a first insulator material disposed between the first conductive structure and the second conductive structure, wherein the first insulator material comprises high gain insulator material (42 may comprise silicon oxynitride ¶0038); and
Chanda fails to explicitly teach a cooling structure operable to remove heat from the capacitively coupled device to achieve an operating temperature at or below 0°C.
Mayberry teaches a device similar to that of Chanda, and explicitly teaches a cooling structure for chips suitable for removing heat to achieve an operating temperature at or below 0°C (¶0045).
Use of external cooling structures to cool chips was known to those having ordinary skill in the art and the combination of such a structure into the die of Chanda would have been obvious.
As to claim 2: Chanda + Mayberry teaches the IC die of claim 1. Chanda teaches the die further comprising:
a first dielectric layer with the first conductive structure embedded therein (50 above layer 42); and
a second dielectric layer vertically adjacent to the first dielectric layer with the second conductive structure embedded therein, wherein the second conductive structure is vertically aligned with the first conductive structure (20).
As to claim 3: Chanda + Mayberry teaches the IC die of claim 1. Chanda further teaches wherein one or more of the first conductive structure and the second conductive structure comprises a metal material (63 is metal ¶0045).
As to claim 4: Chanda + Mayberry teaches the IC die of claim 1. Chanda further teaches wherein the high gain insulator material comprises a high-k oxide material (42 may comprise silicon oxynitride ¶0038).
As to claim 5: Chanda + Mayberry teaches the IC die of claim 1. Chanda teaches the die further comprising:
second insulator material in contact with the first conductive structure and the second conductive structure, wherein the second insulator material comprises lower gain insulator material as compared to the first insulator material (22 may contain air, which has lower dielectric constant than silicon oxynitride).
As to claim 6: Chanda + Mayberry teaches the IC die of claim 5. Chanda teaches the die further comprising:
a third conductive structure in contact with the second insulator material (left-most 33 in contact with air cavity 22), wherein the third conductive structure is proximate to the first conductive structure and vertically spaced further from the first conductive structure as compared to the second conductive structure (conductive structures proximate, further vertically from 63 than right-most 33 is).
Claim(s) 7-10 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chanda, Mayberry, and US 20250357247 (Or-Bach).
As to claim 7: Chanda teaches a system, comprising:
a substrate (Chanda Fig 6, 10);
an integrated circuit (IC) die attached to the substrate, the IC die comprising a first conductive structure for a terminal of a capacitively coupled device (33), a second conductive structure aligned with the first conductive structure for a signal to be capacitively coupled to the terminal of the capacitively coupled device (right-most 33; these lines necessarily capacitively coupled), and a first insulator material disposed between the first conductive structure and the second conductive structure, wherein the first insulator material comprises high gain insulator material (42 may comprise silicon oxynitride ¶0038)
Chanda fails to explicitly teach a power supply or a cooling structure.
Mayberry teaches a device similar to that of Chanda, and explicitly teaches a cooling structure for chips suitable for removing heat to achieve an operating temperature at or below 0°C (¶0045). It would have been obvious for the same reasons as those presented in the claim 1 rejection to combine Chanda and Mayberry.
Still, Chanda + Mayberry fails to explicitly teach a power supply.
Or-Bach teaches a system similar to that of Chanda and Mayberry, explicitly teaching connection to external devices such as a power supply (¶0098).
It would have been obvious to include the power supply of Or-Bach with the system of Chanda + Mayberry in order to allow the device to run in the first place.
As to claim 8: Chanda + Mayberry + Or-Bach teaches the system of claim 7. Chanda teaches wherein the IC die further comprises:
a first dielectric layer with the first conductive structure embedded therein (50 above layer 40); and
a second dielectric layer vertically adjacent to the first dielectric layer with the second conductive structure embedded therein, wherein the second conductive structure is vertically aligned with the first conductive structure (20).
As to claim 9: Chanda + Mayberry + Or-Bach teaches the system of claim 7. Chanda teaches the system further comprising:
second insulator material in contact with the first conductive structure and the second conductive structure, wherein the second insulator material comprises lower gain insulator material as compared to the first insulator material (22 may contain air, which has lower dielectric constant than silicon oxynitride).
As to claim 10: Chanda + Mayberry + Or-Bach teaches the system of claim 9. Chanda teaches the system further comprising:
a third conductive structure in contact with the second insulator material (left-most 33 in contact with air cavity 22), wherein the third conductive structure is proximate to the first conductive structure and vertically spaced further from the first conductive structure as compared to the second conductive structure (conductive structures proximate, further vertically from 63 than right-most 33 is).
As to claim 13: Chanda + Mayberry + Or-Bach teaches the system of claim 7, but fails to explicitly teach wherein the signal comprises one of a data path signal and a processor data bus signal. However, the device of claim 7 is capable of comprising either of the claimed signals and such was known to those having ordinary skill in the art at the time of filing.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chanda + Mayberry + Or-Bach as applied to claim 7 above, and further in view of US 20230125395 (Gao).
As to claim 11: Chanda + Mayberry + Or-Bach teaches the system of claim 7 but fails to explicitly teach wherein the capacitively coupled device is in one of front-side and back-side layers of the IC die.
Gao teaches a system in which a capacitively coupled device is in one of a front-side and back-side layer of an IC die (Gao Fig 2A, 204/206 coupled through IC 203)
All of the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of applicant’s filing.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chanda + Mayberry + Or-Bach as applied to claim 7 above, and further in view of US 20190095568 (Bezzam).
As to claim 12: Chanda + Mayberry + Or-Bach teaches the system of claim 7 but fails to explicitly teach wherein the capacitively coupled device is part of a domino circuit.
Bezzam teaches a system in which a capacitively coupled device is utilized as part of a domino logic die (Bezzam, abstract).
All of the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of applicant’s filing.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chanda + Mayberry + Or-Bach as applied to claim 7 above, and further in view of US 20190348345 (Parida).
As to claim 14: Chanda + Mayberry + Or-Bach teaches the system of claim 7, but fails to explicitly teach details of the metallization layers or of the cooling structure. However, such IC dies necessarily contain layers of metallization capable of providing signal routing.
Parida teaches a system in which a cooling system is over an IC die (Parida Fig 1, structures 112 over die).
All of the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of applicant’s filing.
As to claim 15: Chanda + Mayberry + Or-Bach + Parida teaches the system of claim 14. Parida, as applied to claim 14, further teaches wherein the cooling structure comprises a plurality of microchannels in the IC die and over the plurality of metallization layers, the microchannels to convey a heat transfer fluid therein (channels 112 with fluid 114).
As to claim 16: Chanda + Mayberry + Or-Bach + Parida teaches the system of claim 15. Parida, as applied to claim 15, further teaches wherein the cooling structure further comprises a chiller mounted to the IC die over the microchannels, the chiller comprising one of a solid body comprising second microchannels to convey a second heat transfer fluid therein or a heat sink for immersion in a low-boiling point liquid (122 contains second channels 126 with second fluid 128).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corbyn D Mellinger whose telephone number is (703)756-5683. The examiner can normally be reached M-F 9-6 Eastern.
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/Corbyn D Mellinger/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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