Prosecution Insights
Last updated: July 17, 2026
Application No. 17/955,266

Resource Use Orchestration for Multiple Application Instances

Final Rejection §101§102
Filed
Sep 28, 2022
Examiner
DOSHI, ANKIT B
Art Unit
3715
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Amd
OA Round
4 (Final)
67%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
372 granted / 557 resolved
-3.2% vs TC avg
Strong +22% interview lift
Without
With
+21.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
36 currently pending
Career history
596
Total Applications
across all art units

Statute-Specific Performance

§101
21.6%
-18.4% vs TC avg
§103
46.7%
+6.7% vs TC avg
§102
21.4%
-18.6% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 557 resolved cases

Office Action

§101 §102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/30/2026 has been entered. Applicant’s submission of a response on 3/30/2026 has been received and considered. In the response, Applicant amended claims 1, 2, 6 – 11, 13, 15 and 21 - 23; cancelled claims 12, 14 and 16 – 20; and added new claims 26 and 27. Therefore, claims 1 – 11, 13, 15, 21 – 27 are pending. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 11, 13, 15, 21 – 23 and 25 – 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Poddar et al. (US Pub. No. 2021/0240546 A1). As per claim 1, Poddar et al. discloses a method comprising: controlling, by at least one processor, access to a graphics processing unit configured for sharing by a plurality of containers that execute a plurality of instances of a shared application environment (can mitigate scheduling issues for multiple concurrent workloads… this can include approaches to data or content streaming that enable streaming service providers to provide a higher and more consistent quality of end user experience to streaming clients by mitigating scheduling issues inherent to multi-streaming platforms, see [0018]) by: dividing a time interval for accessing the graphics processing unit into multiple respective time slots (see [0024] and [0030]); assigning each of the plurality of containers to one of the multiple respective time slots in a predetermined order according to a disbursement algorithm (assigning each container to a unique staggered position within the VSYNC interval using a “power of two” disbursement algorithm that operated in a predetermined order, see [0029] - [0032]); and causing the plurality of containers to access the graphics processing unit in the predetermined order by providing, to each container, a respective signal offset specifying a respective assigned time slot when the container is to access the graphics processing unit (providing a respective signal offset to each container specifying when it is to access the GPU, see Fig. 5 and [0038]). As per claim 2, Poddar et al. discloses the respective signal offset is based on an offset from a baseline signal specifying a first respective time slot in the predetermined order that a first container is to access the graphics processing unit (the VSync interval, the first stream is assigned a VSync signal at the start of the interval — time t1 — which constitutes the "baseline signal, see [0030]). As per claim 3, Poddar et al. discloses the disbursement algorithm causes the plurality of containers to be assigned in the predetermined order to evenly spaced time slots over the time interval (see [0029] - [0032]). As per claim 4, Poddar et al. discloses the disbursement algorithm is configured based on a binary tree (a process can also attempt to maintain this phase shift between the clients. The initial offset can be remembered, where that offset may have been computed by random method or binary division or other such methods. Since this is a software-generated VSync signal, this signal may not be precise due to factors such as OS scheduling delays, see [0031]). As per claim 5, Poddar et al. discloses each of the multiple respective time slots is associated with an offset factor according to the disbursement algorithm, and wherein the respective signal offset is determined based on the offset factor (The power-of-two algorithm associates each container/stream with a specific fractional offset factor within the VSync interval (e.g., 0, 1/2, 1/4, 3/4, etc., as shown in FIG. 4A), and the signal offset for each container is determined by multiplying that offset factor by the VSync period, see Fig. 4A – 5 and [0029] – [0032]). As per claim 6, Poddar et al. discloses assigning the plurality of containers to the graphics processing unit based on computing devices of the plurality of containers having same refresh rate or frame per second criteria (VSync-based synchronization scheme is predicated on all participating containers sharing a common display refresh rate, as VSync signals are by definition tied to a common frame rate (FPS) cycle, see [0018] and [0025]). As per claim 7, Poddar et al. discloses determining the time interval for accessing the graphics processing unit with a consistent refresh rate among the computing devices (See [0026[ - [0028]). As per claim 8, Poddar et al. discloses the time interval is divided into the multiple respective time slots based on a maximum number of containers supported by the graphics processing unit during the time interval (the number of available time slots within a VSync interval is determined by the number of streams/containers that the GPU-based system can support. The granularity of the slot division is a direct function of the maximum number of supported containers, as each container requires one dedicated slot, see [0020] – [0024]). As per claim 9, Poddar et al. discloses the respective signal offset is provided to each of the plurality of containers to access the graphics processing unit in the predetermined order by sequentially submitting respective commands to the graphics processing unit (See Fig. 5 and [0038]). As per claim 10, Poddar et al. discloses the graphics processing unit executes the respective commands when the respective commands are submitted to the graphics processing unit (see [0021]). As per claim 11, the instant claim is a system in which corresponds to the method of claim 1. Therefore, it is rejected for the reasons set forth above. As per claim 13, Poddar et al. discloses the shared application environment comprises a shared gaming application environment and each of the plurality of containers is one of a plurality of instances of the shared gaming application environment (see [0037]). As per claim 15, Poddar et al. discloses the respective signal offset is provided to each of the plurality of containers to access the graphics processing unit in the predetermined order by sequentially submitting respective commands to the graphics processing unit, and wherein the graphics processing unit executes the respective commands when the respective commands are submitted to the shared resource graphics processing unit (See Fig. 5 and [0038]). As per claim 21, Poddar et al. discloses each of the plurality of containers executes a respective instance of the shared application environment by accessing the graphics processing unit, and the plurality of containers execute each instance of the shared application environment by accessing the graphics processing unit based on commands from a respective computing device from a plurality of computing devices in communication with the at least one processor (See Fig. 1 and [0019] and [0038]). As per claim 22, Poddar et al. discloses causing the plurality of containers to access the graphics processing unit in the predetermined order causes consistent quality of service of the shared application environment across the plurality of computing devices (see [0021] and [0036]). As per claim 23, Poddar et al. discloses the plurality of containers to access the graphics processing unit in the predetermined order regulates consistent latencies between the graphics processing unit and the plurality of computing devices (the staggered ordering of GPU access regulates and equalizes latency for all client devices, see [0025] and [0036]). As per claim 25, Poddar et al. discloses dividing the time interval into the multiple respective time slots comprises dividing the time interval into the evenly spaced time slots, and each evenly spaced time slot corresponds to one of the multiple respective time slots (see [0029] - [0032]). As per claim 26, Poddar et al. discloses causing the plurality of containers to access the graphics processing unit in the predetermined order regulates the graphics processing unit to not switch to a reduced-power or idle state between sequential container accesses (see [0025]). As per claim 27, Poddar et al. discloses causing the plurality of containers to access the graphics processing unit in the predetermined order further regulates consistent latencies between the graphics processing unit and the plurality of computing devices (the staggered ordering of GPU access regulates and equalizes latency for all client devices, see [0025] and [0036]). Examiner’s Note Claim 24 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Poddar et al. does not expressly disclose executing the disbursement algorithm by: inputting to the binary tree a number of the plurality of containers and the time interval; calculating respective offset factors for the plurality of containers based on respective positions of the plurality of containers within the binary tree; outputting respective signal offsets for the plurality of containers by multiplying the respective offset factors by the time interval; and associating each of the multiple respective time slots with one of the respective offset factors. Response to Arguments Applicant’s arguments, see p. 7 - 13, filed on 3/30/2026, with respect to the rejection(s) of claim(s) 1 – 15 and 21 – 25 under 35 USC 101 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Poddar et al. (US Pub. No. 2021/0240546 A1). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANKIT B DOSHI whose telephone number is (571)270-7863. The examiner can normally be reached Mon - Fri. ~8:30 - ~5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dmitry Suhol can be reached at 571-272-4430. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANKIT B DOSHI/Examiner, Art Unit 3715
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Prosecution Timeline

Show 5 earlier events
Aug 29, 2025
Response Filed
Dec 29, 2025
Final Rejection mailed — §101, §102
Mar 10, 2026
Applicant Interview (Telephonic)
Mar 30, 2026
Request for Continued Examination
Apr 10, 2026
Response after Non-Final Action
Apr 21, 2026
Non-Final Rejection mailed — §101, §102
Jun 05, 2026
Response Filed
Jul 14, 2026
Final Rejection mailed — §101, §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
67%
Grant Probability
88%
With Interview (+21.7%)
3y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 557 resolved cases by this examiner. Grant probability derived from career allowance rate.

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