DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 21, 22, 24, 26-29, 31, and 33-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okutsu et al. (WO 2021/199447, see US 2023/0156997) in view of Cheah et al. (US 2013/0341803).
Regarding claim 1, Okutsu et al. discloses, as shown in Figures 1-21, an apparatus comprising:
a first integrated circuit (IC) die (21) comprising front surface, a back surface, a first side surface, a second side surface opposite the first side surface;
a second IC die (21) comprising front surface, a back surface, a first side surface, a second side surface opposite the first side surface;
a substrate (10) coupled to the first side surface of the first IC die and the first side surface of the second IC die, the substrate extending in a second orientation substantially orthogonal to the first orientation;
fill material (40) between the first IC die and the second IC die;
interconnect layers (29) over the second side surface of the first IC die and the second IC die, the interconnect layers comprising metallization lines in the second orientation; and
a metal via (24) extending from the metallization lines of the interconnect layers, through the second side surface of the first IC die to the first IC die.
Okutsu et al. does not disclose the plurality of IC dies having the respective metallization structures. However, Cheah et al. discloses a plurality of IC dies having the respective metallization structures (138, 144). Note Figures 1A-3I of Cheah et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the plurality of IC dies of Okutsu et al. having the respective metallization structures, such as taught by Cheah et al. in order to provide interconnection/signal input/output between the internal circuit and the input/output terminals.
Regarding claim 2, Okutsu et al. and Cheah et al. disclose the apparatus further comprising a second metal via extending from the metallization of the interconnect layers, through the second side surface of the second IC die, to a second metallization structure of the second IC die, wherein the metal via and the second metal via are coupled by the metallization lines of the interconnect layer.
Regarding claim 24, Okutsu et al. discloses, as shown in Figures 1-21, an apparatus comprising:
a reconstituted wafer comprising a plurality of integrated circuit (IC) dies (21) coupled to a substrate of the reconstituted wafer on respective first sidewalls of the plurality of IC dies;
one or more interconnect layers (10, 29) over the reconstituted wafer and coupled to respective second sidewalls the plurality of IC dies opposite the respective first sidewalls, wherein the one or more interconnect layers provide one or more electrical connections between two or more IC dies, of the plurality of IC dies;and
a plurality of metal connections (24) extending from the one or more interconnect layers, through the respective second sidewalls to the plurality of IC dies.
Okutsu et al. does not disclose the plurality of IC dies having the respective metallization structures. However, Cheah et al. discloses a plurality of IC dies having the respective metallization structures (138, 144). Note Figures 1A-3I of Cheah et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the plurality of IC dies of Okutsu et al. having the respective metallization structures, such as taught by Cheah et al. in order to provide interconnection/signal input/output between the internal circuit and the input/output terminals.
Regarding claims 5, 26 and 33, Okutsu et al. and Cheah et al. disclose a bond between the interconnect layers and the respective second sidewalls of the plurality of IC dies.
Note that the term “hybrid bond” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 27, Okutsu et al. and Cheah et al. disclose the plurality of metal connections extend orthogonal to the respective metallization structures.
Regarding claims 21 and 28, Okutsu et al. and Cheah et al. disclose a wafer-scale engine comprises the plurality of IC dies, the one or more interconnection layers, and the plurality of metal connections.
Regarding claims 22 and 29, Okutsu et al. and Cheah et al. disclose the apparatus further comprising:
an IC package comprising the plurality of IC dies, the one or more interconnect layers, and the plurality of metal connections; and
a power supply coupled to the IC package.
Regarding claim 31, Okutsu et al. and Cheah et al. disclose the apparatus further comprising:
an IC package comprising the plurality of IC dies (21), the one or more interconnect layers, and the plurality of metal connections; and
a power supply coupled to the IC package.
Regarding claim 31, Okutsu et al. discloses, as shown in Figures 1-21, an apparatus comprising:
a plurality of integrated circuit (IC) dies (21) comprising front, back, and side surfaces;
one or more interconnect layers (10, 29) coupled to the side surfaces of the IC die, wherein the one or more interconnect layers provide one or more electrical connections between the plurality of IC dies; and
a plurality of metal connections (24) extending from the one or more interconnect layers, through the side surfaces of the plurality of IC dies to the plurality of IC dies.
Okutsu et al. does not disclose the plurality of IC dies having the respective metallization structures. However, Cheah et al. discloses a plurality of IC dies having the respective metallization structures (138, 144). Note Figures 1A-3I of Cheah et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the plurality of IC dies of Okutsu et al. having the respective metallization structures, such as taught by Cheah et al. in order to provide interconnection/signal input/output between the internal circuit and the input/output terminals.
Regarding claim 34, Okutsu et al. and Cheah et al. disclose a wafer-scale engine comprises the plurality of IC dies, the one or more interconnection layers, and the plurality of metal connections.
Regarding claim 35, Okutsu et al. and Cheah et al. disclose the apparatus further comprising:
an IC package comprising the plurality of IC dies (21), the one or more interconnect layers, and the plurality of metal connections; and
a power supply coupled to the IC package.
Claim(s) 3, 23, 25, 30, 32 and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okutsu et al. (WO 2021/199447, see US 2023/0156997) in view of Cheah et al. (US 2013/0341803) and further in view of Patel et al. (US 2021/0407879).
Regarding claims 3, 25, and 32, Okutsu et al. and Cheah et al. do not disclose a plurality of microchannels laterally adjacent to the one or more interconnect layers, the plurality of microchannels to convey a heat transfer fluid therein. However, Patel et al. disclose a plurality of microchannels (256) in the IC device and over the reconstituted wafer, the microchannels to convey a heat transfer fluid therein (Figures 2-4 and 6). Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the apparatus of Okutsu et al. and Cheah et al. having a plurality of microchannels laterally adjacent to the one or more interconnect layers, the plurality of microchannels to convey a heat transfer fluid therein, such as taught by Patel et al. in order to remove the heat from the device.
Regarding claims 23, 30 and 36, Okutsu et al. and Cheah et al. disclose the claimed invention including the system as explained in the above rejection. Okutsu et al. and Cheah et al. do not disclose a cooling structure coupled to the IC device operable to remove heat from the IC device. Patel et al. also discloses the apparatus comprising a cooling structure (204, 228, 232, 240, 256, 404, 436, 464, 604, etc.) coupled to the IC device (132, 136, 140, 144, 148) operable to remove heat from the IC device with the achieved operating temperature. Note Figures 2-6 and 6 of Patel et al. Okutsu et al., Cheah et al., and Patel et al. do not disclose the claimed operating temperature. However, it is a recitation of intended use of the claimed invention. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the apparatus of Okutsu et al. and Cheah et al. having the cooling structure coupled to the IC device, such as taught by Patel et al. in order to further remove the heat from the device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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