DETAILED ACTION
Claims 1, 4-11, 14-21, and 24-25 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not sufficiently descriptive of the claimed invention. A new title is required that is clearly indicative of the invention to which the claims are directed. At this point in time, the examiner recommends --FAR JUMP INSTRUCTIONS ENABLED BY COMPATIBILITY CONTROL REGISTER BITS--.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In original paragraph 55, in line 5, “return” does not appear to be the correct word in this sentence. Please correct without adding new matter.
In amended paragraph 57, 2nd to last line, insert a spec between “21” and “provide”.
In original paragraph 67, line 3, replace “[NAME OF]”.
In original paragraph 67, last line, insert --an-- before “absolute”.
In original paragraph 185, at least some of applicant’s examples are substantially similar to the claims and suffer from the same issues pointed out previously and/or below.
In original paragraph 185, in example 23, replace “an far” with --a far--.
Appropriate correction is required.
Drawings
FIGs.3-4 are objected to because of the following minor informalities:
In FIG.3, for bit 38, insert --INTRASEGMENT-- after “ENABLE” to better make clear the difference between the descriptions of bits 37 and 38.
In FIG.4, step 407, the examiner does not understand the purpose of all language starting with “AND…” in line 2, as it merely repeats that in step 401. The examiner recommends deletion of this language.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections/Recommendations
Claim 1 (and similarly each of claims 11 and 21) is objected to because of the following informalities:
In line 7, insert --the-- after “wherein”.
The last line is grammatically incorrect, assuming applicant wants the execution circuitry to be part of the claimed apparatus. If so, the examiner recommends claiming either --the execution circuitry, which is to execute…-- or --the execution circuitry, to execute…--. If, however, applicant intends for the last line to be part of the “wherein…”, then applicant should insert a colon after “wherein” in line 7 and include indented paragraphs for the remaining limitations.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6 and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 5 (and similarly in claims 15 and 25), “the instruction” because it could refer to the single instruction or decoded instruction. Please insert --single-- as was done in claim 6 and other claims.
Claims 6 and 16 are further rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-11, 14-21, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Neiger et al. (US 2022/0283813 A1), in view of Seconi et al. (US 5,619,726). In addition, Felix Cloutier, “CALL - Call Procedure” (herein “Felix”) is cited as extrinsic evidence showing encoding details of the x86 CALL instruction.
Referring to claim 1, Neiger has taught an apparatus comprising:
decoder circuitry (FIG.1, decoder 109) to decode an instance of a single instruction (FIG.15, step 1501, FAR CALL instruction, which is decoded (paragraph 230)), the single instruction to include at least one field for an opcode and one or more fields for an operand, wherein the opcode is to indicate execution circuitry is to perform a far jump and the operand is to specify an address to be jumped to (paragraphs 228 and 232), wherein an operand size attribute of the instance of the instruction is 32-bit or greater (paragraph 232) and the instruction has been enabled by a setting of a bit in a compatibility control register (see paragraphs 106 and 234-235. FRED may be enabled by setting a bit in a control register CR4. When a FAR CALL makes use of a call gate, this instruction is enabled when FRED is disabled; otherwise, a protection fault occurs); and
execution circuitry (FIG.1, execution units 109) to execute the decoded instruction according to the opcode to perform a far jump (FIG.15, step 1507) and the operand is to specify an address to be jumped to, wherein an operand size attribute of the instance of the instruction is 32-bit or greater and the instruction has been enabled by a setting of a bit in a compatibility control register, wherein compatibility control register includes a first bit to enable a far jump instruction (see the rejection of the previous paragraph of claim 1), a second bit to enable an intrasegment far jump instruction (there are at least 32 bits in CR4 (since paragraph 106 refers to setting bit 32 in CR4). Any other bit set in a particular way that doesn’t disable an intrasegment far jump would be the second bit. In other words, as long as setting some other bit in CR4 doesn’t result in disabling such a far jump, it enables the intrasegment far jump. Additionally, any FAR CALL may execute, and this includes a FAR CALL to a same segment, which is possible when the current code segment matches the code segment identified by the FAR CALL operand. Thus, intrasegment far calls would be enabled (even if not necessarily performed, which the claim does not require))).
Neiger has not taught that the compatibility control register includes a third bit to enable an interrupt return instruction. However, Seconi has taught a control register that includes an EIR bit that enables a return from interrupt instruction to restart a halted transfer (see column 19, TABLE D-2, bit 0). This bit, as explained in the TABLE, column 1, line 66, to column 2, line 8, column 12, lines 56-65, and column 13, line 57, to column 14, line 2, allows for DMA that was interrupted by a time-critical task to be automatically resumed upon execution of a return from interrupt instruction. DMA has known advantages in the art such as performing memory operations independently of a CPU, thereby freeing up the CPU to do other work. Having this bit allows for returning from interrupt to restart the DMA after it was interrupted for high-priority work. Otherwise, the DMA would have to be manually restarted, which may require extra programming by a user. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Neiger to include interruptible DMA (to handle memory operations and allow for prioritizing time-critical work) and a control bit to enable to the return from interrupt to resume the DMA after interruption. In the combination, it would have been obvious to include this third bit in CR4 in Neiger, where the other control bits are, as the examiner asserts that the location of the bit is not a patentable distinction, particularly where applicant has not demonstrated the criticality of the location of the third bit (see MPEP 2144.04 for relevant case law).
Referring to claim 4, Neiger, as modified, has taught the apparatus of claim 1. Though Neiger has not explicitly taught wherein the one or more fields for an operand include a ModR/M field, Felix has taught that an x86 indirect FAR CALL (to which Neiger is directed) is encoded using a ModR/M field (see the top table and note that the indirect far calls have the opcode encoding ‘M’, which, from the next table, is shown to include a ModR/M operand).
Referring to claim 5, Neiger, as modified, has taught the apparatus of claim 1. Further taught is wherein the one or more fields for an operand include a ModR/M field (see the rejection of claim 4). Though Neiger has not explicitly taught that the one or more fields for an operand include a bit in a prefix of the instruction, Neiger does teach a REX prefix (FIG.37 and paragraph 447), and Felix has taught that the REX prefix W bit may be used to indicate an operand (see the last row in the top table of Felix).
Referring to claim 6, Neiger, as modified, and Felix, have taught the apparatus of claim 5, wherein the bit in the prefix of the single instruction is to indicate a 64-bit operand (see Felix, top table, last row).
Referring to claim 7, Neiger, as modified, has taught the apparatus of claim 1, wherein the single instruction is only valid in a 32-bit user mode, a 64-bit user mode, and a supervisor mode (see Felix, top table, and note the FAR CALL can be used in 32-bit and 64-bit modes. Also, from paragraph 116 of Neiger, note that far calls that use call gates increase privilege, and, from paragraph 89, increasing privilege results in supervisor mode (which are at rings 0, 1, or 2). No other mode is mentioned in conjunction with a FAR CALL).
Referring to claim 8, Neiger, as modified, has taught the apparatus of claim 1, wherein the one or more fields for an operand include 6-byte immediate (see paragraph 232).
Referring to claim 9, Neiger, as modified, has taught the apparatus of claim 1, wherein the far jump is an absolute jump using direct addressing (paragraph 232).
Referring to claim 10, Neiger, as modified, has taught the apparatus of claim 1, wherein the far jump is an absolute jump using indirect addressing (paragraph 232).
Claim 11 is mostly rejected for similar reasoning as claim 1. Further, Neiger has taught memory to store an instance of a single instruction (see paragraph 416, which discloses fetching instructions from memory. Such a memory could be 114 (FIG.1), instruction cache 3234 (FIG.32B), etc.).
Claims 14-20 are rejected for similar reasoning as claims 4-10, respectively.
Claims 21 and 24-25 are directed to a method performed by the system of claims 1 and 4-5, respectively. Thus, claims 21 and 24-25 are rejected for similar reasoning as claims 1 and 4-5, respectively.
Response to Arguments
On page 13 of applicant’s response, applicant states that paragraph 185 has not been amended to maintain the original examples.
The objection is maintained. Clear grammatical/typographical issues need to be fixed.
On page 13 of the response, applicant states that the original language of FIG.4 (step 407) would be retained because it is the same as that in step 401 and the applicant is unsure how its removal would be interpreted by a court.
The examiner does not understand this argument. If the exact same language is to be retained in step 401, then how would updated step 407 be interpreted differently? The examiner is merely proposing to eliminate redundancy.
On page 14 of the response, applicant argues that the claim language requires three distinct bits to affirmatively enable three different types of instructions, and that CR4 already has other bits and a PHOSITA would not interpret any other bit to enable another type of instruction.
While the examiner agrees that Neiger has not taught all three bits, an updated search has revealed Secondi, which teaches the claimed third bit. The examiner asserts that it would be obvious to include this third bit in CR4 in Neiger for reasons set forth in the rejections above. The examiner also notes that the first and second bits do not necessarily enable different types of instructions (they may enable the same intrasegment far jump instruction). Finally, the examiner notes that if a particular type of jump is allowed to occur, then it is allowed to occur in response to all current system conditions (this includes the state of all bits in CR4). The examiner recommends claiming that the second bit is to disable an intrasegment far jump as opposed to enable. A bit being set in a way to enable (not stop) an instruction is different from one specifically dedicated to disabling that instruction.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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