DETAILED ACTION
Claims 1-25 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraph 167, the examples include substantially similar language to the original and current claims. Please correct similarly to the claims. For instance, in example 7, the word “mode” is clearly missing”, and, in examples 12-20, applicant is referring to the system of example 11, which sets forth an apparatus, not a system.
Appropriate correction is required.
Drawings
Replacement FIG.3 is objected to because of the following minor informalities:
In step 305, there is a lack of basis for “THE SOURCE OPERAND(S)”.
Step 307 is grammatically incorrect and must be reworded. Specifically, “A FIRST EXECUTION MODE APPLICATIONS” is grammatically incorrect.
Replacement FIG.3 is objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The drawings are pixelated, likely because applicant did not use black (RGB = 000), despite the drawings appearing black to the naked eye. In such a case, the dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. Applicant may attempt the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat Pro DC (a similar Adobe product may work, but the examiner has only tested this in Adobe Acrobat Pro DC);
2. Click “File” and then click “Print”;
3. Select “Adobe PDF” as the printer. If not available, “Microsoft Print to PDF” may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck “Print in grayscale (black and white)”;
5. Uncheck “Save ink/toner”;
6. Click “Advanced”;
7. Under “Color Management”, for the “Color Profile” field, select “Black & White” near the bottom of the list. The examiner also had “Treat grays as K-only grays” checked, and “Preserve Black” checked.
8. Click “OK” and then click “Print”. The resulting PDF should comprise only black and white drawings. Please review the final drawings for potential unintended consequences of this process.
A corrected drawing sheet in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections/Recommendations
Referring to each of claims 1 and 11, although the examiner understands the claim, one might perceive a lack of basis related to “the execution circuitry to execute the decoded instruction…”. Thus, the examiner recommends separating “the execution circuitry” and its action, which is not previously set forth. For instance, the examiner recommends --the execution circuity, which is configured to…--.
Claims 12-20 are objected to because of the following informalities:
Each of these claims sets forth “The system of claim…”, which lacks basis. Change “system” to --apparatus-- in each instance. Alternatively, applicant may change “apparatus” to --system-- in claim 11.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 11-16, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wikipedia, “CPUID” (herein referred to as Wikipedia1). Furthermore, Wikipedia, “x86-64” (herein referred to as Wikipedia2) is cited as extrinsic evidence showing operating characteristics of an x86-64 processor taught by Wikipedia1.
Referring to claim 1, Wikipedia1 has taught an apparatus (from p.1, 1st paragraph, Wikipedia is related to a processor having the x86 architecture) comprising:
decoder circuitry to decode an instance of a single instruction (a processor includes decoder circuitry to decode the CPUID instruction that is the topic of the Wikipedia1 article), the single instruction to include at least one field for an opcode (the instruction includes an opcode field that stores the binary value (0F A2H, per p.1) corresponding to “CPUID”), the opcode to indicate execution circuitry is to return processor identification and feature information determined by input into a first register and a second register (the value of register EAX (and, optionally, the value of ECX) dictate(s) the registers to which data will be returned, and which data will be returned. For instance, on pp.3-5, when the EAX input = 1, the EAX, EBX, ECX, and EDX registers (two of which may be first and second registers) are all set with various identification and feature information for a processor. Alternatively, from pp.7-9, when EAX=7 and ECX=0 (these may be the first and second registers into which inputs are stored), registers EBX, ECX, and EDX are loaded with processor identification and feature information. Alternatively, from pp.9-10, when EAX=7 and ECX=1 (first and second register inputs), identification and feature information are returned to EAX),
wherein the processor identification and feature information is to include an indication of an availability of a second execution mode that at least deprecates features of a first execution mode (the processor executing CPUID may be a 64-bit x86 processor (p.3, paragraph above the code snippet). Thus, a second mode made available is a 64-bit mode that includes the combination of enabled features returnable by a CPUID instruction. Any feature turned off would be a deprecated feature that would be part of a first mode that would have that feature enabled. Note also that bit 13 in EBX on p.8 is for feature deprecation. Thus, when this bit is set for a 64-bit processor, the second mode would be a 64-bit mode that deprecates FPU CS and FPU DS, which would be available in a first mode that doesn’t deprecate these features (e.g. used by a different processor). As another example, when bit 17 on p.10 is disabled, FRED is deprecated (i.e., second mode would be a 64-bit mode without FRED, where the first mode would be a 64-bit mode with FRED (or even just a FRED mode)); and
the execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including the indication of the availability of the second execution mode that is to only natively support 64-bit system software and only natively support 32-bit and 64-bit applications using the registers (a processor includes execution circuitry to carry out the operation of CPUID, which again is to return data to one or more registers based on at least one input register. Further, a 64-bit processor only natively supports 64-bit operating system (OS) software (in long, non-protected mode) (see Wikipedia2, p.7). While a 32-bit or 16-bit OS may be supported, they are not natively supported because the 64-bit processor must execute in legacy (non-native) mode to run them (see Wikipedia2, p.7). Additionally, the 64-bit processor only natively supports 32-bit and 64-bit applications because these applications execute in long, non-protected mode (“native” mode) (see Wikipedia2, p.7). Again, 16-bit applications may be executed, but not natively, since they must execute in a protected mode (see p.7 of Wikipedia2)).
Referring to claim 2, Wikipedia1 has taught the apparatus of claim 1, wherein the opcode is OF A2H (see p.1, first sentence under the “Calling CPUID” heading).
Referring to claim 3, Wikipedia1 has taught the apparatus of claim 1, wherein the first register is EAX and the second register is ECX (see the end of p.7, which shows executing CPUID based on a first register being EAX and a second register being ECX. Also, see the end of p.9).
Referring to claim 4, Wikipedia1 has taught the apparatus of claim 1, wherein a value to be stored in the first register is 07H and a value to be stored in the second register is 01H (see the end of p.9).
Referring to claim 5, Wikipedia1 has taught the apparatus of claim 1, wherein the execution circuitry is to return the indication of the availability of the second execution mode by writing the second register, wherein bit positions of the second register are to indicate particular functionalities (see pp.5 and 7-8, where numerous bit positions of the second register (ECX) may be set to ‘1’ or ‘0’ to indicate corresponding functionalities. For example, on p.8, bit 19 of ECX relates to address width adjustment by particular MMX instructions in 64-bit mode).
Referring to claim 6, Wikipedia1 has taught the apparatus of claim 5, wherein bit position 19 is used to indicate the availability of the second execution mode (see p.8, where bit 19 of EBX indicates whether Intel ADX is enabled. So, whether this is ‘0’ or ‘1’, it contributes to the overall definition of the second mode (e.g. if it is set, one can say the a second mode including Intel ADX functionality is available). Alternatively, on p.8, a different mode is realized based on whether bit 19 is ‘0’ or ‘1’ since it would define a different width for address adjustment. So, setting bit 19 would indicate availability of a mode whose address adjustment is the value X, and non-availability of a mode whose address adjustment is not X).
Claim 11 is mostly rejected for similar reasoning as claim 1. Wikipedia1 has further taught a memory to store an instance of a single instruction (instructions (program code) are stored in memory so as to be fetched by a processor for execution. For instance, the code shown on p.3, including a CPUID instruction, would be stored in memory).
Claims 12-16 and 21-23 are rejected for similar reasoning as claims 2-6, 1, 3, and 5, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8, 17-18, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Wikipedia1 in view of Branco (US 2020/0019403 A1).
Referring to claim 7, Wikipedia1 has taught the apparatus of claim 1, wherein the return of the processor identification and feature information including the indication of the availability of the second execution mode that at least deprecates features of the first execution mode is to further explicitly return information regarding one or more legacy features of the first execution mode (since the data accessed by CPUID is actually stored in result registers, the data can be said to be explicitly returned to those registers. Also, note that a number of bits may be related to legacy features. For instance, on p.5, SSE, SSE2, and SSE4.1 are prior to SSE4.2 (and thus are legacy features with respect to SSE4.2). Note that other bits throughout may be legacy-related. For instance, on p.15, bit 4 is for use of CR8 in 32-bit mode, where 32-bit mode is a legacy mode compared to 64-bit mode)
Wikipedia1 has not taught that the one or more legacy features are disabled in the second execution mode. However, Branco has taught flexible disabling of features to reduce customer cost for those that don’t require the features (paragraph 25), for export compliance (paragraph 24), and/or for security reasons (paragraphs 24 and 27). As such, one of ordinary skill in the art would have recognized that for any given processor, any combination of features may be enabled/disabled based for one of the above reasons (e.g. to increase security, or to lower purchase cost). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wikipedia1 such that the one or more legacy features are disabled in the second execution mode.
Referring to claim 8, Wikipedia1 has taught the apparatus of claim 1, wherein the return of the processor identification and feature information including the indication of the availability of the second execution mode that at least deprecates features of the first execution mode is to further implicitly return information regarding one or more legacy features of the first execution mode (from paragraph 53 of applicant’s specification, an implicit return appears to include not explicitly identifying input registers in the instruction’s encoding. Such is the case in Wikipedia1, on p.3, where the CPUID instruction itself (5th instruction after the “main:” label) includes no explicit operands. Note that a number of bits may be related to legacy features. For instance, on p.5, SSE, SSE2, and SSE4.1 are prior to SSE4.2 (and thus are legacy features with respect to SSE4.2). Note that other bits throughout may be legacy-related. For instance, on p.15, bit 4 is for use of CR8 in 32-bit mode, where 32-bit mode is a legacy mode compared to 64-bit mode).
Wikipedia1 has not taught that the one or more legacy features are disabled in the second execution mode. However, Branco has taught flexible disabling of features to reduce customer cost for those that don’t require the features (paragraph 25), for export compliance (paragraph 24), and/or for security reasons (paragraphs 24 and 27). As such, one of ordinary skill in the art would have recognized that for any given processor, any combination of features may be enabled/disabled based for one of the above reasons (e.g. to increase security, or to lower purchase cost). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wikipedia1 such that the one or more legacy features are disabled in the second execution mode.
Claims 17-18 and 24-25 are rejected for similar reasoning as claims 7-8 and 7-8, respectively.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wikipedia1 in view of Intel, “IA-64 Application Developer’s Architecture Guide”, and the examiner’s taking of Official Notice.
Referring to claim 9, Wikipedia1 has taught the apparatus of claim 1, wherein the execution circuitry is to load the processor identification and feature information into the registers to be used for the return of the processor identification and feature information (again, see the rejection of claim 1). Wikipedia1 has not taught that the identification and feature information is from non-volatile memory. However, Intel teaches that the data to be returned is stored in CPUID registers, which are fixed with data specific to that processor. The registers are read-only via a move instruction (to move data to a general register, much like the CPUID instruction). See p.3-10 through 3-12 (section 3.1.11) and 4-32. While being fixed doesn’t necessarily equate to being non-volatile, Official Notice is taken that non-volatile memory was well known in the art before applicant’s invention. Non-volatile memory keeps its contents even when power is removed. Thus, it would not need to be reloaded every time the computer is powered down, which results in time savings. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wikipedia1 such that the identification and feature information is from non-volatile memory.
Claim 19 is rejected for similar reasoning as claim 9.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wikipedia1 in view of Intel, Cepulis (US 6,223,271), and the examiner’s taking of Official Notice.
Referring to claim 10, Wikipedia1 has taught the apparatus of claim 1, wherein the execution circuitry is to load the processor identification and feature information into the registers to be used for the return of the processor identification and feature information (again, see the rejection of claim 1). Wikipedia1 has not taught that the identification and feature information is from volatile memory written to by a basic input/output system (BIOS). However, Intel has taught that the information that CPUID accesses originates in fixed CPUID registers (p.3-10 through 3-12 (section 3.1.11)). While Intel has not taught that the CPUID registers are written to by BIOS, Cepulis has taught that upon booting or reset, a BIOS can load a control register within the processor to provide control during processing (see column 2, lines 54-63). One of ordinary skill in the art would have recognized that by allowing a BIOS to load features into the CPUID registers, the features can be flexibly changed over time as desired (for instance, a BIOS update can occur which enables/disables different features, or adds new features, etc.). Additionally, implementing registers in volatile memory was well known in the art before applicant’s invention. Volatile memory is generally faster than non-volatile memory and, thus, such an implementation for the control register would be desirable when speed is a priority. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wikipedia1 such that the identification and feature information is from volatile memory written to by a basic input/output system (BIOS).
Claim 20 is rejected for similar reasoning as claim 10.
Response to Arguments
On page 17 of applicant’s response, applicant argues that the references has not taught decode or execution circuitry.
The examiner respectfully disagrees. Wikipedia is related to executing a CPUID instruction in an x86 processor. Such a processor must use decode circuitry to decode an instruction to determine the operation to perform, and then perform that operation using execution circuitry.
On page 17 of applicant’s response, applicant argues that the prior art does not disclose deprecated features, i.e., the taking away of features. Applicant states that, in the prior art, a feature may not exist, but it is not taken away.
This is not persuasive. The examiner does not see how applicant’s claim language distinguishes from the teachings of Wikipedia. As stated in the rejection of claim 1, any feature turned off would be a deprecated feature, which would be part of a first mode having that feature enabled. Again, bit 13 in EBX on p.8 is literally for deprecation. When this bit is set for a 64-bit processor, the second mode would be a 64-bit mode that deprecates (takes away) FPU CS and FPU DS, which would be available in a first mode that doesn’t deprecate these features (e.g. used by a different processor). As another example, when bit 17 on p.10 is disabled, FRED is deprecated (i.e., second mode would be a 64-bit mode without FRED, where the first mode would be a 64-bit mode with FRED (or even just a FRED mode)).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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