Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Restriction/Election
Applicant’s election of Claims 1-3 and 6-20 in the reply filed on 9/30/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 1 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Walter (CN 102273029, machine-translation provided)
Regarding Claim 1
FIG. 11 of Walter discloses an optoelectronic device, comprising a substrate (1105); a bottom electrode (1120) at a top surface of the substrate; a plurality of semiconducting layers (1130-1170) deposited over the bottom electrode and the substrate; and a top electrode (1170) deposited over the plurality of semiconducting layers, wherein the plurality of semiconducting layers forms a bipolar junction transistor (BJT) between the bottom electrode and the top electrode, the top electrode and the bottom electrode are a collector electrode and an emitter electrode of the BJT, the BJT includes a collector (1130) that is contacting the collector electrode, the BJT includes an emitter (1150/1160) that is contacting the emitter electrode, and the semiconducting layers include a BJT base (1140) formed at least in part using a quantum dot layer [0016].
Claims 1, 2 and 7-13 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. Patent Pub. No. 2022/0278228)
Regarding Claim 1
FIG. 13 of Kim discloses an optoelectronic device, comprising a substrate (1301); a bottom electrode (1302) at a top surface of the substrate; a plurality of semiconducting layers (1303-1307) deposited over the bottom electrode and the substrate; and a top electrode (1308) deposited over the plurality of semiconducting layers, wherein the plurality of semiconducting layers forms a bipolar junction transistor (BJT) between the bottom electrode and the top electrode, the top electrode and the bottom electrode are a collector electrode and an emitter electrode of the BJT, the BJT includes a collector (1303) that is contacting the collector electrode, the BJT includes an emitter (1307) that is contacting the emitter electrode, and the semiconducting layers include a BJT base formed at least in part using a quantum dot layer (1305).
Regarding Claim 2
Kim discloses light absorbed by one of the semiconducting layers produces a current that is amplified by the BJT [0173]. Furthermore, the recitation “light absorbed by one of the semiconducting layers produces a current that is amplified by the BJT” is only a statement of the inherent properties of the device. When the structure recited in the prior art is substantially identical to that of the claimed invention, then the claimed properties or functions are presumed to be inherent. Or where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01.
Regarding Claim 7
FIG. 13 of Kim discloses the bottom electrode (1302) is a back side reflector configured to reflect at least 45% infrared light.
Regarding Claim 8
FIG. 13 of Kim discloses the top electrode is configured to pass infrared light into the optoelectronic device [0163].
Regarding Claim 9
FIG. 13 of Kim discloses the top electrode is configured to pass at least 50% of normally incident infrared light into the optoelectronic device.
Regarding Claim 10
FIG. 13 of Kim discloses a first one of the semiconducting layers is deposited over the bottom electrode and the substrate; a second one of the semiconducting layers is deposited over the first one of the semiconducting layers; a third one of the semiconducting layers is deposited over the second one of the semiconducting layers; and the second one of the semiconducting layers is a photoactive region that absorbs photons and produces charge carriers [0191].
Regarding Claim 11
FIG. 13 of Kim discloses a first one of the semiconducting layers is deposited over the bottom electrode and the substrate; a second one of the semiconducting layers is deposited over the first one of the semiconducting layers; a third one of the semiconducting layers is deposited over the second one of the semiconducting layers; and the second one of the semiconducting layers is configured to produce a plurality of charge carriers from a plurality of photons within an infrared wavelength range [0133].
Regarding Claim 12
FIG. 13 of Kim discloses a first one of the semiconducting layers is deposited over the bottom electrode and the substrate; a second one of the semiconducting layers is deposited over the first one of the semiconducting layers; a third one of the semiconducting layers is deposited over the second one of the semiconducting layers; and the second one of the semiconducting layers is configured to produce a plurality of charge carriers from a plurality of photons within a wavelength range; and the bottom electrode (DBR) is configured to reflect the photons in the wavelength range.
Regarding Claim 13
FIG. 13 of Kim discloses the top electrode (1309) is configured to pass the photons (1310) in the wavelength range into the optoelectronic device.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 6 and 20 rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Jain (U.S. Patent Pub. No. 2012/0280208), in view of Guyot (WO 2020160370).
Regarding Claim 3
Kim discloses Claim 1, wherein: a first one (1304) of the semiconducting layers is P-type deposited over the bottom electrode and the substrate; a second one of the semiconducting layers is deposited over the first one of the semiconducting layers; a third one (QD) of the semiconducting layers is deposited over the second one of the semiconducting layers; and the third one of the semiconducting layers is a P-type quantum dot layer [0038].
Kim is silent with respect to “the first one of the semiconducting layers is a P-type polysilicon layer; the second one of the semiconducting layers is a N-type metal oxide layer”.
FIG. 7a of Jain discloses a similar optoelectronic device, wherein: the first one (60) of the semiconducting layers is a P-type polysilicon layer; the second one (31) of the semiconducting layers is a metal oxide layer; and the third one (30) of the semiconducting layers is a quantum dot layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Jain. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of reducing defects ([0003] of Jain).
Kim as modified by Jain is silent with respect to “the second one of the semiconducting layers is a N-type metal oxide layer”.
FIG. 1 of Guyot discloses a similar optoelectronic device, wherein: a first one (150) of the semiconducting layers is deposited over the bottom electrode and the substrate; a second one (160) of the semiconducting layers is deposited over the first one of the semiconducting layers; a third one (170) of the semiconducting layers is deposited over the second one of the semiconducting layers; the first one of the semiconducting layers is a P-type layer [0025]; the second one of the semiconducting layers is a N-type metal oxide layer [0027]; and the third one of the semiconducting layers is a P-type quantum dot layer
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Guyot. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of multi-spectral sensing capability ([0003] of Guyot).
Regarding Claim 6
FIG. 1 of Guyot discloses the semiconducting layers include a P-type quantum dot layer; and the P-type quantum dot layer that is a HgTe quantum dot layer [0010].
Regarding Claim 20
FIG. 13 of Kim discloses method comprising: obtaining a substrate (1301) that has a bottom electrode (1302) at a top surface of the substrate; depositing a plurality of semiconducting layers (1303-1307) over the bottom electrode and the substrate; and depositing a top electrode (1308) over the plurality of semiconducting layers, wherein the plurality of semiconducting layers forms a bipolar junction transistor (BJT) between the bottom electrode and the top electrode, the top electrode and the bottom electrode are a collector electrode and an emitter electrode of the BJT, the BJT includes a collector (1303) that is contacting the collector electrode, the BJT includes an emitter (1307) that is contacting the emitter electrode, the plurality of semiconducting layers includes a P-type quantum dot layer (1305).
Kim is silent with respect to “the second one of the semiconducting layers is a N-type metal oxide layer”.
FIG. 1 of Guyot discloses a similar optoelectronic device, wherein: the second one of the semiconducting layers is a N-type metal oxide layer [0027].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Kim, as taught by Guyot. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of multi-spectral sensing capability ([0003] of Guyot).
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Walter, in view of Jain, in view of Guyot (WO 2020160370).
Regarding Claim 3
Walter discloses Claim 1, comprising a p+n layer 1631 adjacent to the p-type quantum dot layer.
Walter is silent with respect to “the first one of the semiconducting layers is a P-type polysilicon layer; the second one of the semiconducting layers is a N-type metal oxide layer”.
FIG. 7a of Jain discloses a similar optoelectronic device, wherein: the first one (60) of the semiconducting layers is a P-type polysilicon layer; the second one (31) of the semiconducting layers is a metal oxide layer; and the third one (30) of the semiconducting layers is a quantum dot layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Walter, as taught by Jain. The ordinary artisan would have been motivated to modify Walter in the above manner for purpose of reducing defects ([0003] of Jain).
Walter as modified by Jain is silent with respect to “the second one of the semiconducting layers is a N-type metal oxide layer”.
FIG. 1 of Guyot discloses a similar optoelectronic device, wherein: a first one (150) of the semiconducting layers is deposited over the bottom electrode and the substrate; a second one (160) of the semiconducting layers is deposited over the first one of the semiconducting layers; a third one (170) of the semiconducting layers is deposited over the second one of the semiconducting layers; the first one of the semiconducting layers is a P-type layer [0025]; the second one of the semiconducting layers is a N-type metal oxide layer [0027]; and the third one of the semiconducting layers is a P-type quantum dot layer
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Walter, as taught by Guyot. The ordinary artisan would have been motivated to modify Walter in the above manner for purpose of multi-spectral sensing capability ([0003] of Guyot).
Claims 14 and 15 rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Nam (U.S. Patent Pub. No. 2009/0146197).
Regarding Claim 14
Kim discloses Claim 1.
Kim is silent with respect to “the substrate includes a read-out integrated circuit (ROIC) and an array of bottom electrodes configured as a plurality of input pads of the ROIC; the bottom electrodes include the bottom electrode; the semiconducting layers and the top electrode form a plurality of BJTs; and the BJTs form a focal plane array of an image sensor”.
FIG. 3 of Nam discloses a similar optoelectronic device, wherein: the substrate includes a read-out integrated circuit (ROIC) (220) and an array of bottom electrodes configured as a plurality of input pads of the ROIC; the bottom electrodes include the bottom electrode; the semiconducting layers and the top electrode form a plurality of BJTs; and the BJTs form a focal plane array of an image sensor
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Nam. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of improving the detection efficiency and signal response speed (Abstract of Nam).
Regarding Claim 15
Kim discloses light absorbed by one of the semiconducting layers produces a current that is amplified by the BJTs [0161].
Claims 18 rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Nam (U.S. Patent Pub. No. 2009/0146197), in view of Guyot (WO 2020160370).
Regarding Claim 18
FIG. 13 of Kim discloses an optoelectronic device, comprising a substrate (1301); an array of input pads; a plurality of semiconducting layers (1303-1307) deposited over the input pads (1302) and the substrate; and a top electrode (1308) deposited over the plurality of semiconducting layers, wherein the plurality of semiconducting layers forms a bipolar junction transistor (BJT) between the bottom electrode and the top electrode, the top electrode and the bottom electrode are a collector electrode and an emitter electrode of the BJT, the BJT includes a plurality of collectors (1307) and a plurality of emitters (1307), the top electrode and the input pads are collector electrodes and emitter electrodes of the BJTs, the collectors are contacting the collector electrodes, the emitters are contacting the emitter electrodes, the semiconducting layers include a P-type quantum dot layer (1305). the semiconducting layers include a N-type metal oxide layer, and the BJTs form a focal plane array of an image sensor
Kim is silent with respect to “a read-out integrated circuit (ROIC) that includes an array of input pads” and “the semiconducting layers include a N-type metal oxide layer, and the BJTs form a focal plane array of an image sensor”.
FIG. 3 of Nam discloses a similar optoelectronic device, wherein: the substrate includes a read-out integrated circuit (ROIC) (220) and an array of bottom electrodes configured as a plurality of input pads of the ROIC; the bottom electrodes include the bottom electrode; the semiconducting layers and the top electrode form a plurality of BJTs; and the BJTs form a focal plane array of an image sensor
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Nam. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of improving the detection efficiency and signal response speed (Abstract of Nam).
Kim as modified by Nam is silent with respect to “the semiconducting layers include a N-type metal oxide layer”.
FIG. 1 of Guyot discloses a similar optoelectronic device, wherein: a first one (150) of the semiconducting layers is deposited over the bottom electrode and the substrate; a second one (160) of the semiconducting layers is deposited over the first one of the semiconducting layers; a third one (170) of the semiconducting layers is deposited over the second one of the semiconducting layers; the first one of the semiconducting layers is a P-type layer [0025]; the second one of the semiconducting layers is a N-type metal oxide layer [0027]; and the third one of the semiconducting layers is a P-type quantum dot layer
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Guyot. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of multi-spectral sensing capability ([0003] of Guyot).
Claims 14-17 rejected under 35 U.S.C. 103 as being unpatentable over Walter, in view of Ohzu (EP 0693786).
Regarding Claim 14
Walter discloses Claim 1.
Walter is silent with respect to “the substrate includes a read-out integrated circuit (ROIC) and an array of bottom electrodes configured as a plurality of input pads of the ROIC; the bottom electrodes include the bottom electrode; the semiconducting layers and the top electrode form a plurality of BJTs; and the BJTs form a focal plane array of an image sensor”.
FIG. 15 of Ohzu discloses a similar optoelectronic device, wherein: the substrate includes a read-out integrated circuit (ROIC) (4) and an array of bottom electrodes configured as a plurality of input pads of the ROIC; the bottom electrodes include the bottom electrode; the semiconducting layers and the top electrode form a plurality of BJTs; and the BJTs form a focal plane array of an image sensor (bipolar type sensors).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Walter, as taught by Ohzu. The ordinary artisan would have been motivated to modify Walter in the above manner for purpose of outputting signal from each pixel sequentially (text of Ohzu).
Regarding Claim 15
Ohzu discloses light absorbed by one of the semiconducting layers produces a current that is amplified by the BJTs.
Regarding Claim 16
FIG. 13 of Walter discloses the semiconducting layers stay unpatterned.
Regarding Claim 17
FIG. 13 of Walter discloses the semiconducting layers and the top electrode stay unpatterned.
Claims 18-20 rejected under 35 U.S.C. 103 as being unpatentable over Walter, in view of Nam, in view of Tachibana (JP 2008287900, machine-translation provided).
Regarding Claim 18
FIG. 11 of Walter discloses an optoelectronic device, comprising a substrate (1105); an array of input pads (1120); a plurality of semiconducting layers (1130-1170) deposited over the input pads and the substrate; and a top electrode (1170) deposited over the plurality of semiconducting layers, wherein the plurality of semiconducting layers forms a bipolar junction transistor (BJT) between the bottom electrode and the top electrode, the top electrode and the bottom electrode are a collector electrode and an emitter electrode of the BJT, the BJT includes a plurality of collectors (1130) and a plurality of emitters (1150/1160), the top electrode and the input pads are collector electrodes and emitter electrodes of the BJTs, the collectors are contacting the collector electrodes, the emitters are contacting the emitter electrodes, the semiconducting layers include a P-type quantum dot layer (1141).
Walter is silent with respect to “a read-out integrated circuit (ROIC) that includes an array of input pads” and “the semiconducting layers include a N-type metal oxide layer, and the BJTs form a focal plane array of an image sensor”.
FIG. 3 of Nam discloses a similar optoelectronic device, wherein: the substrate includes a read-out integrated circuit (ROIC) (220) and an array of bottom electrodes configured as a plurality of input pads of the ROIC; the bottom electrodes include the bottom electrode; the semiconducting layers and the top electrode form a plurality of BJTs; and the BJTs form a focal plane array of an image sensor
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Walter, as taught by Nam. The ordinary artisan would have been motivated to modify Walter in the above manner for purpose of improving the detection efficiency and signal response speed (Abstract of Nam).
Walter as modified by Nam is silent with respect to “the semiconducting layers include a N-type metal oxide layer”.
Tachibana discloses a similar optoelectronic device, wherein: the semiconducting layers include a N-type metal oxide layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Walter, as taught by Tachibana. The ordinary artisan would have been motivated to modify Walter in the above manner for purpose of providing a photoelectric transfer element having very high current transfer rate (Abstract of Tachibana).
Regarding Claim 19
FIG. 13 of Walter discloses the semiconducting layers and the top electrode stay unpatterned.
Regarding Claim 20
FIG. 11 of Walter discloses a method comprising: obtaining a substrate (1105) that has a bottom electrode (1120) at a top surface of the substrate; depositing a plurality of semiconducting layers (1130-1170) over the bottom electrode and the substrate; and depositing a top electrode (1170) over the plurality of semiconducting layers, wherein the plurality of semiconducting layers forms a bipolar junction transistor (BJT) between the bottom electrode and the top electrode, the top electrode and the bottom electrode are a collector electrode and an emitter electrode of the BJT, the BJT includes a plurality of collectors (1130) and a plurality of emitters (1150/1160), the top electrode and the input pads are collector electrodes and emitter electrodes of the BJTs, the collectors are contacting the collector electrodes, the emitters are contacting the emitter electrodes, the semiconducting layers include a P-type quantum dot layer (1141).
Walter is silent with respect to “the semiconducting layers include a N-type metal oxide layer, and the BJTs form a focal plane array of an image sensor”.
Tachibana discloses a similar optoelectronic device, wherein: the semiconducting layers include a N-type metal oxide layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Walter, as taught by Tachibana. The ordinary artisan would have been motivated to modify Walter in the above manner for purpose of providing a photoelectric transfer element having very high current transfer rate (Abstract of Tachibana).
Pertinent Art
FIG. 17 of Imamura (U.S. Patent No. 5,936,258), discloses an optoelectronic device comprising: a substrate (45); a bottom electrode (52) at a top surface of the substrate; a plurality of semiconducting layers (46-50) deposited over the substrate; and a top electrode (51) deposited over the plurality of semiconducting layers, wherein the plurality of semiconducting layers forms a bipolar junction transistor (BJT) between the bottom electrode and the top electrode, the top electrode and the bottom electrode are a collector electrode (52) and an emitter electrode (51) of the BJT, the BJT includes a collector (46) that is contacting the collector electrode, the BJT includes an emitter (50) that is contacting the emitter electrode, and the semiconducting layers include a BJT base formed at least in part using a quantum dot layer (48). FIG. 2 of Chaudhry (U.S. Patent Pub. No. 2003/0052721)discloses a optoelectronic device, comprising a substrate (200); a bottom electrode (206) at a top surface of the substrate; a plurality of semiconducting layers (210-220) deposited over the bottom electrode and the substrate; and a top electrode (241) deposited over the plurality of semiconducting layers, wherein the plurality of semiconducting layers forms a bipolar junction transistor (BJT) between the bottom electrode and the top electrode, the top electrode and the bottom electrode are a collector electrode (206) and an emitter electrode (241) of the BJT, the BJT includes a collector (234) that is contacting the collector electrode, the BJT includes an emitter (235) that is contacting the emitter electrode. Other pertinent art includes US 20090115346, CN 101238619, CN 117866762 and WO 2009051664.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897