Prosecution Insights
Last updated: July 17, 2026
Application No. 17/955,476

NETWORK-ON-CHIP (NoC) USING DEADLINE BASED ARBITRATION

Non-Final OA §103
Filed
Sep 28, 2022
Priority
Sep 28, 2021 — provisional 63/249,033
Examiner
UNELUS, ERNEST
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Arteris Inc.
OA Round
4 (Non-Final)
77%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
422 granted / 546 resolved
+22.3% vs TC avg
Strong +39% interview lift
Without
With
+39.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
19 currently pending
Career history
574
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
57.8%
+17.8% vs TC avg
§102
40.0%
+0.0% vs TC avg
§112
0.3%
-39.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 546 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . RESPONSE TO AMENDMENT Claim rejections based on prior art Applicant's arguments filed on 03/23/2026 with respect to claims 1, 4-8, 10, 11, 14-18 and 20-21 have been fully considered but are moot in view of newly cited reference. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 103 1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 2. Claim 1, 4-8, 10, 11, 14-18 and 20-21 is rejected under 35 U.S.C. 103(a) as being unpatentable over Ishii et al. (US pub. # 2015/0052283), hereinafter, “Ishii”, in view of Morimoto et al. (US pub. # 2011/ 0138092), hereinafter, “Morimoto”, and further in view of Foo (US pub. # 2020/0110557), hereinafter, “Foo”. At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references. 3. As pers claim 1, 11 and 21, Ishii discloses a method of deadline arbitration in a network-on-chip (NoC) (SoC 200 of fig. 4) in communication with an initiator and a target (see paragraph 0067, which discloses “FIG. 4 illustrates the structure of an SoC 200 in which a plurality of initiators and a plurality of memories are connected together via an NoC”), the method comprising: creating, using a deadline creation module, a deadline for packet delivery from the initiator to the target (see paragraphs 0047 and 0076); wherein the deadline represents a maximum amount of time to travel from the initiator to the target along a path (please note, this limitation is only reciting what the deadline ‘represents’, just a functional language) (see paragraph 0080, which discloses “the deadline information field 51-5 stores a value to be obtained based on the latency which is permitted until data of a response packet is replied to the initiator in response to a request packet”), wherein the path includes a plurality of switches and each switch includes a local arbitration scheme (see figs. 1 and 4); generating, at a packet creating module, a packet that includes the deadline (see paragraphs 0047 and 0076), wherein the deadline is stored in a header of the packet as a time-value (see paragraph 0047, which discloses “a header generator which generates a packet header that stores the corrected deadline time information”, paragraph 0076, which discloses “FIG. 6 illustrates an exemplary format for the packet header 51, which may include a packet ID field 51-1, a packet type field 51-2, a source field 51-3, a destination field 51-4, a deadline information field 51-5, and a data size field 51-6, for example. The header may further include fields to store any other pieces of information” and paragraph 0080, which discloses “the deadline information field 51-5 stores a value to be obtained based on the latency which is permitted until data of a response packet is replied to the initiator in response to a request packet”); and selecting the packet, with a packet routing module (see paragraph 0092), to route within the NoC along the path using at least the deadline for arbitration (note, claim ‘arbitration’ is being equated to the function of transmission of packets) between the packet and other packets being routed by the NoC (see paragraph 0099, which discloses “when there is contention between multiple packets over the same output port, the arbiter 211 compares the pieces of deadline information that are stored in the respective headers of those contending packets to each other, and applies a router arbitration rule so that the output port is allocated to the packet with the earliest deadline time first”). Ishii fails to disclose wherein arbitration wait time, which is due to the packet having lost arbitration at one switch of the plurality of switches along the path, influences a next arbitration at a next switch of the plurality of switches as the packet travels along the path and the time-value is adjusted based on the arbitration wait time. Morimoto discloses wherein arbitration wait time (please note, Applicant’s filed specification doesn’t disclose the phrase ‘arbitration wait time’), which is due to the packet having lost arbitration at one switch of the plurality of switches along the path, influences a next arbitration at a next switch of the plurality of switches as the packet travels along the path (see abstract of Morimoto teaching a packet losing arbitration due to having a second highest priority and moving up to the top priority at a next hop, arbitration device, after a wait time). Foo discloses the time-value is adjusted based on the arbitration wait time [see paragraph 0121, which discloses “this timestamp may be adjusted for propagation delay by a fixed offset”, paragraph 0136, which discloses “header addition 638 appends a custom header at the beginning of each packet. The contents of the custom header may be similar or the same as that of the PCAP per-packet header 303. In alternative embodiments, the header may be 16 bytes in length and may consist of one or more of the following fields: a NOP field that may be set when the packet contains NOP data from NOP generator 612, a frame check sequence (FCS) fail flag that may be set when the FCS the packet's Ethernet header indicates a corrupted packet, a pad flag that may be set when the chunk contains padding from padder 636, a timestamp field that may contain the time (in nanoseconds and sourced from delimiter 604) of when the packet was captured, a packet capture size field that may indicate the number of bytes of the packet that were actually captured, a packet wire size field that may indicate the actual size of the packet prior to capture, and a portID field that may identify the physical port on which the packet was received” and paragraph 0221]. It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to modified Morimoto’s teaching of a hierarchical arbitration system with an arbitration device at each level of the hierarchy to select a resource use request having the highest priority and a resource use request having the second highest priority, and Foo’s teaching of an embodiment of non-volatile memory configured to store chunks of data packets, wherein the chunks are associated with sequence numbers, into Ishii’s teaching of an interface apparatus connecting an initiator that is arranged on an integrated circuit and a bus network that has been formed on the integrated circuit, for the benefits of reducing an occurrence of a bubble phenomenon even in a system in which a master does not repeatedly issue identical memory use requests. 4. As per claims 4 and 14, the combination of Ishii, Morimoto and Foo discloses “The method of claim 1” [See rejection to claim 1 above], further comprising readjusting the deadline by subtracting from the deadline, wherein arbitration is determined by selecting from one or more packets with a smallest deadline (see paragraph 0117 of Ishii and paragraph 0221 of Foo, which discloses “rewriting the timestamps of the data packets”). 5. As per claims 5 and 15, Ishii discloses wherein routing the packet includes selecting the packet with the deadline closest to a target deadline value when arbitrating (see paragraph 0099). 6. As per claims 6 and 16, Ishii discloses wherein the packet includes a priority (deadline information, as discloses in paragraph 0099) and routing the packet includes using the deadline (deadline time, as discloses in paragraph 0099) and the priority (see paragraph 0099). 7. As per claims 7 and 17, the combination of Ishii, Morimoto and Foo discloses “The method of claim 6” [See rejection to claim 6 above], wherein routing packet includes adjusting deadline by an amount based on the priority when waiting on arbitration (see paragraph 0099 of Ishii and paragraph 0221 of Foo). 8. As per claims 8 and 18, the combination of Ishii, Morimoto and Foo discloses “The method of claim 1” [See rejection to claim 1 above], wherein the deadline is set to a reserved value and arbitration is lost to one or more packets that have the respective deadlines set to a value other than the reserved value (see paragraph 0099 of Ishii and abstract of Morimoto). 9. As per claims 10 and 20, the combination of Ishii, Morimoto and Foo discloses “The method of claim 1” [See rejection to claim 1 above], further comprising: adjusting deadline at target while waiting on a response after the packet has arrived at a destination; creating a response that includes the deadline at the target; and routing the response to the initiator using the deadline (see paragraphs 0051 and 0117 of Ishii and paragraphs 0121, 0136 and 0221 of Foo). CLOSING COMMENTS Conclusion a. STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i): a(1) CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1, 4-8, 10, 11, 14-18 and 20-21 have received a final action on the merits. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. b. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ernest Unelus whose telephone number is (571) 272-8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM. IMPORTANT NOTE If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /Ernest Unelus/ Primary Examiner Art Unit 2181
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Prosecution Timeline

Show 9 earlier events
Nov 06, 2025
Response after Non-Final Action
Dec 23, 2025
Non-Final Rejection mailed — §103
Feb 23, 2026
Interview Requested
Mar 03, 2026
Applicant Interview (Telephonic)
Mar 03, 2026
Examiner Interview Summary
Mar 23, 2026
Response Filed
Apr 22, 2026
Final Rejection mailed — §103
Jun 22, 2026
Response after Non-Final Action

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Prosecution Projections

4-5
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+39.0%)
3y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 546 resolved cases by this examiner. Grant probability derived from career allowance rate.

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