DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al (US Publication no. 2020/0075719).
Regarding claim 1, Cheng discloses an integrated circuit structure, comprising: a sub-fin structure beneath a stack of nanowires Fig 2B, the stack of nanowires Fig 3B, 112, 114, 116 having a first end and a second end; a dielectric cap Fig 9A, 120 having a first portion vertically over the first end of the stack of nanowires and having a second portion vertically over the second end of the stack of nanowires Fig 9A, 112, 114, 116, wherein the dielectric cap Fig 9A, 120 is not vertically over a location between the first end and the second end of the stack of nanowires Fig 9A, 120; a gate electrode Fig 9A or Fig 10, 162 and Fig 10, 210 over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap Fig 9A; and a gate dielectric structure Fig 9A and Fig 10, 160 between the gate electrode and the stack of nanowires¶0078 Fig 9A and Fig 10.
Regarding claim 2, Cheng discloses wherein the gate electrode is in direct contact with the first and second portions of the dielectric cap Fig 9A-11 ¶0077-0078.
Regarding claim 4, Cheng discloses wherein the sub-fin structure is a semiconductor sub-fin structure Fig 3A-3B, Fig 9A-11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Publication no. 2020/0075719) in view of Guler et al (US Publication No. 2020/0219978).
Regarding claim 5, Cheng discloses all the limitations but silent on the insulator sub fin. Whereas Guler discloses wherein the sub-fin structure is an insulator sub-fin structure Fig 6, 698. Cheng and Guler are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Cheng and incorporate the teachings of Guler to improve device isolation.
Claims 6-7, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Publication no. 2020/0075719) in view of Adam et al (US Publication No. 2014/0346612).
Regarding claim 6, Cheng discloses an integrated circuit structure, comprising: a sub-fin structure beneath a stack of nanowires Fig 2B, the stack of nanowires Fig 3B, 112, 114, 116 having a first end and a second end; a dielectric cap Fig 9A, 120 having a first portion vertically over the first end of the stack of nanowires and having a second portion vertically over the second end of the stack of nanowires Fig 9A, 112, 114, 116, wherein the dielectric cap Fig 9A, 120 is not vertically over a location between the first end and the second end of the stack of nanowires Fig 9A, 120; a gate electrode Fig 9A or Fig 10, 162 and Fig 10, 210 over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap Fig 9A; and a gate dielectric structure Fig 9A and Fig 10, 160 between the gate electrode and the stack of nanowires¶0078 Fig 9A and Fig 10. Cheng discloses all the limitations but silent on the channel shape. Whereas Adam discloses a fin having a first end and a second end Fig 8B-8C; a dielectric cap Fig 8B-8C, 46 having a first portion vertically over the first end of the fin and having a second portion vertically over the second end of the fin Fig 8B-8C, a gate electrode Fig 8B-8C, 52 over the fin and laterally between the first and second portions of the dielectric cap; and a gate dielectric structure between the gate electrode and the fin Fig 8B-8C. Cheng and Adam are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Cheng and incorporate the teachings of Adam as an alternative channel shape known in the art and since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 7, Cheng discloses wherein the gate electrode is in direct contact with the first and second portions of the dielectric cap Fig 9A-11 ¶0077-0078.
Regarding claim 9, Cheng discloses wherein the sub-fin structure is a semiconductor sub-fin structure Fig 3A-3B, Fig 9A-11.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Publication no. 2020/0075719) and Adam et al (US Publication No. 2014/0346612) in further view of Guler et al (US Publication No. 2020/0219978).
Regarding claim 10, Cheng discloses all the limitations but silent on the insulator sub fin. Whereas Guler discloses wherein the sub-fin structure is an insulator sub-fin structure Fig 6, 698. Cheng and Guler are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Cheng and incorporate the teachings of Guler to improve device isolation.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Mannebach et al (US Publication no. 2020/0219970) in view of Cheng et al (US Publication no. 2020/0075719).
Regarding claim 11, Mannebach discloses a computing device, comprising: a board Fig 10; and a component coupled to the board Fig 10, the component including an integrated circuit structure, comprising: a sub-fin structure beneath a stack of nanowires Fig 3A, the stack of nanowires Fig 3A, 304A-304C, 314A-314C having a first end and a second end; a gate electrode Fig 3A, 308 over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap ¶0056; and a gate dielectric structure Fig 3D, 370 between the gate electrode and the stack of nanowires Fig 3D. Mannebach discloses all the limitations but silent on the arrangement of the dielectric cap. Whereas Cheng discloses an integrated circuit structure, comprising: a sub-fin structure beneath a stack of nanowires Fig 2B, the stack of nanowires Fig 3B, 112, 114, 116 having a first end and a second end; a dielectric cap Fig 9A, 120 having a first portion vertically over the first end of the stack of nanowires and having a second portion vertically over the second end of the stack of nanowires Fig 9A, 112, 114, 116, wherein the dielectric cap Fig 9A, 120 is not vertically over a location between the first end and the second end of the stack of nanowires Fig 9A, 120; a gate electrode Fig 9A or Fig 10, 162 and Fig 10, 210 over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap Fig 9A; and a gate dielectric structure Fig 9A and Fig 10, 160 between the gate electrode and the stack of nanowires¶0078 Fig 9A and Fig 10. Mannebach and Cheng are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mannebach because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Mannebach and incorporate the teachings of Cheng to improve device isolation.
Regarding claim 12, Mannebach discloses a memory coupled to the board Fig 10.
Regarding claim 13, Mannebach discloses a communication chip coupled to the board Fig 10.
Regarding claim 14, Mannebach discloses wherein the component is a packaged integrated circuit die Fig 10.
Regarding claim 15, Mannebach discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor Fig 10.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mannebach et al (US Publication no. 2020/0219970) in view of Adam et al (US Publication No. 2014/0346612) and Cheng et al (US Publication no. 2020/0075719).
Regarding claim 16, Mannebach discloses a computing device, comprising: a board Fig 10; and a component coupled to the board Fig 10, the component including an integrated circuit structure, comprising: a sub-fin structure beneath a stack of nanowires Fig 3A, the stack of nanowires Fig 3A, 304A-304C, 314A-314C having a first end and a second end; a gate electrode Fig 3A, 308 over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap ¶0056; and a gate dielectric structure Fig 3D, 370 between the gate electrode and the stack of nanowires Fig 3D. Mannebach discloses all the limitations but silent on the channel shape. Whereas Adam discloses a fin having a first end and a second end Fig 8B-8C; a dielectric cap Fig 8B-8C, 46 having a first portion vertically over the first end of the fin and having a second portion vertically over the second end of the fin Fig 8B-8C, a gate electrode Fig 8B-8C, 52 over the fin and laterally between the first and second portions of the dielectric cap; and a gate dielectric structure between the gate electrode and the fin Fig 8B-8C. Mannebach and Adam are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mannebach because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Mannebach and incorporate the teachings of Adam as an alternative channel shape known in the art and since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Mannebach discloses all the limitations but silent on the arrangement of the dielectric cap. Whereas Cheng discloses an integrated circuit structure, comprising: a sub-fin structure beneath a stack of nanowires Fig 2B, the stack of nanowires Fig 3B, 112, 114, 116 having a first end and a second end; a dielectric cap Fig 9A, 120 having a first portion vertically over the first end of the stack of nanowires and having a second portion vertically over the second end of the stack of nanowires Fig 9A, 112, 114, 116, wherein the dielectric cap Fig 9A, 120 is not vertically over a location between the first end and the second end of the stack of nanowires Fig 9A, 120; a gate electrode Fig 9A or Fig 10, 162 and Fig 10, 210 over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap Fig 9A; and a gate dielectric structure Fig 9A and Fig 10, 160 between the gate electrode and the stack of nanowires¶0078 Fig 9A and Fig 10. Mannebach and Cheng are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mannebach because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Mannebach and incorporate the teachings of Cheng to improve device isolation.
Regarding claim 17, Mannebach discloses a memory coupled to the board Fig 10.
Regarding claim 18, Mannebach discloses a communication chip coupled to the board Fig 10.
Regarding claim 19, Mannebach discloses wherein the component is a packaged integrated circuit die Fig 10.
Regarding claim 20, Mannebach discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor Fig 10.
Allowable Subject Matter
Claims 3 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811