Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of Species MI without traverse: claims 1-20, in the “Response to Election / Restriction Filed - 12/30/2025”. This office action considers claims 1-20 pending for prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(2):
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 6-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Onogi et al. (US 20240063062 A1 – hereinafter Onogi).
Regarding Claim 6, Onogi teaches an integrated circuit structure (see the entire document; Fig. 10; specifically, [0068]-[0078], and as cited below), comprising:
a gate structure ({50, 52} – Fig. 10 – [0068]) having a gate electrode (52) over a channel structure (35);
a dielectric layer (56 – [0077]) over the gate structure ({50, 52});
a gate contact via (85 – [0079]) in an opening in the dielectric layer (56), the gate contact via in (85) contact with the gate electrode (52 – via 45 – [0076]) of the gate structure ({50, 52}); and
a gate contact via extension (95 – [0078]) on the gate contact via (85), the gate contact via extension (95) above the dielectric layer (56) and extending laterally beyond the gate contact via (Fig. 10 Shows 95 extends laterally beyond 85).
Regarding claim 7, the integrated circuit structure of claim 6, wherein the gate contact via and the gate contact via extension comprise a same metal ([0061]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-3, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20120225558 A1 - hereinafter Chang) in view of Huang et al. (US 20210391184 A1 - hereinafter Huang).
Regarding Claim 1, Chang teaches an integrated circuit structure (see the entire document; annotated Fig. 6F; specifically, ([0007] - [0059]), and as cited below), comprising:
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Chang – annotated Fig. 6F
a trench contact structure (110 – Fig. 6F – [0007]) over a source or drain structure (106 – [0007]);
a dielectric layer (116 – [0040]) over the trench contact structure (110);
a trench contact via (622a – [0059]) in an opening in the dielectric layer (116), the trench contact via (622a) in contact with the trench contact structure (110); and
a trench contact via extension (622b) on the trench contact via (622a), the trench contact via extension (622b) above the dielectric layer (116) and extending laterally beyond the trench contact via (as shown in the annotated Fig. 6F).
But Chang does not expressly disclose that the source or drain structure (106) is epitaxial.
However, it is well known in the art to form source or drain structure by an epitaxial process as is also taught by Huang (Huang – [0015], [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of the source or drain region via an epitaxial process as taught by Huang into Chang.
An ordinary artisan would have been motivated to integrate Huang structure into Chang structure in the manner set forth above for, at least, for the obvious benefit of Controlled Doping Profiles and improved device performance.
Regarding Claim 2, the combination Chang and Huang teaches the integrated circuit structure of claim 1, wherein the trench contact via (Chang 622_a) and the trench contact via extension (622_b) comprise a same metal (since both are part of 622).
Regarding claim 3, the combination Chang and Huang teaches claim 1 from which claim 3 depends.
But the combination does not expressly disclose wherein the trench contact via extension has a substantially flat upper surface.
The instant application specification contains no disclosure of either the critical nature of the claimed relative flatness i.e., “wherein the trench contact via extension has a substantially flat upper surface” or of any unexpected results arising therefrom. Applicant has not disclosed that having a barrier layer thickness of less than 10% of a total thickness, solves any stated problem or is for any particular purpose. "Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies." - In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946), see MPEP 2144.05.III.A.
Regarding claim 8, the combination Onogi teaches claim 6 from which claim 8 depends.
But the combination does not expressly disclose wherein the trench contact via extension has a substantially flat upper surface.
The instant application specification contains no disclosure of either the critical nature of the claimed relative flatness i.e., “wherein the trench contact via extension has a substantially flat upper surface” or of any unexpected results arising therefrom. Applicant has not disclosed that having a barrier layer thickness of less than 10% of a total thickness, solves any stated problem or is for any particular purpose. "Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies." - In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946), see MPEP 2144.05.III.A.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Huang and in further view of Yoon (US 20230127755 A1 – hereinafter Yoon).
Regarding claim 4, the combination Chang and Huang teaches claim 1 from which claim 4 depends. But the combination does not expressly further disclose a conductive line on the trench contact via extension.
However, it is well known in the art to form conductive line on a trench contact extension as is also taught by Yoon (Yoon – in Fig. 2C Yoon teaches a conductive line 61 (61a, 61b – [0029]) over trench contact 30).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of conductive line on a trench contact extension as taught by Yoon into the combination of Chang and Huang.
An ordinary artisan would have been motivated to integrate Yoon structure into the combination of Chang and Huang in the manner set forth above for, at least, for the obvious benefit of routing the source/drain contact to other components as is well known.
Regarding claim 5, the combination Chang, Huang and Yoon teaches the integrated circuit structure of claim 4, wherein the conductive line (Yoon 61a, 61b) comprises a conductive barrier layer (61a) and a conductive fill (61b), the conductive barrier layer conformal with the trench contact via extension (Fig. 2C shows 61a is conformal to 32.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Onogi in view of Yoon.
Regarding claim 9, Onogi teaches claim 6 from which claim 9 depends. But the combination does not expressly further disclose a conductive line on the trench contact via extension.
However, it is well known in the art to form conductive line on a trench contact extension as is also taught by Yoon (Yoon – in Fig. 2C Yoon teaches a conductive line 61 (61a, 61b – [0029]) over trench contact 30.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of conductive line on a trench contact extension as taught by Yoon into Onogi.
An ordinary artisan would have been motivated to integrate Yoon structure into Onogi in the manner set forth above for, at least, for the obvious benefit of routing the source/drain contact to other components as is well known.
Regarding claim 10, the combination Onogi and Yoon teaches the integrated circuit structure of claim 4, wherein the conductive line (Yoon 61a, 61b) comprises a conductive barrier layer (61a) and a conductive fill (61b), the conductive barrier layer conformal with the trench contact via extension (Fig. 2C shows 61a is conformal to 32.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Golonzka et al. (US 20210125866 A1 – hereinafter Golonzka) in view of Chang and in further view of Huang.
Regarding claim 11, Golonzka teaches a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure (Claim 17 – a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure). But Golonzka does not expressly disclose the details of integrated circuit.
However, in a related art Chang teaches:
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Chang – annotated Fig. 6F
a trench contact structure (110 – annotated Fig. 6F – [0007]) over a source or drain structure (106 – [0007]);
a dielectric layer (116 – [0040]) over the trench contact structure (110);
a trench contact via (622a – [0059]) in an opening in the dielectric layer (116), the trench contact via (622a) in contact with the trench contact structure (110); and
a trench contact via extension (622b) on the trench contact via (622a), the trench contact via extension (622b) above the dielectric layer (116) and extending laterally beyond the trench contact via (as shown in the annotated Fig. 6F).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of the details of the integrated circuit as taught by Chang into Golonzka.
An ordinary artisan would have been motivated to integrate Chang structure into Golonzka structure in the manner set forth above for, at least, for the obvious benefit of fabricating a functional integrated circuit as is well known.
But the combination of Golonzka and Chang does not expressly disclose that the source or drain structure (106) is epitaxial.
However, it is well known in the art to form source or drain structure by an epitaxial process as is also taught by Huang (Huang – [0015], [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of the source or drain region via an epitaxial process as taught by Huang into the combination of Golonzka and Chang.
An ordinary artisan would have been motivated to integrate Huang structure into the combination of Golonzka and Chang structure in the manner set forth above for, at least, for the obvious benefit of Controlled Doping Profiles and improved device performance.
Regarding claim 12, the combination of Golonzka, Chang, and Huang teaches the computing device of claim 11, further comprising: a memory coupled to the board (Golonzka – Fig. 5 teaches DRAM, ROM in the motherboard 502.
Regarding claim 13, the combination of Golonzka, Chang, and Huang teaches the computing device of claim 11, further comprising: a communication chip coupled to the board (Golonzka – Fig. 5 teaches communication chip 506 in the motherboard 502).
Regarding claim 14, the combination of Golonzka, Chang, and Huang teaches the computing device of claim 11, further comprising: a camera coupled to the board (Golonzka – [0062]).
Regarding claim 15, the combination of Golonzka, Chang, and Huang teaches the computing device of claim 11, wherein the component is a packaged integrated circuit die (Golonzka – [0064]).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Golonzka in view of Onogi.
Regarding claim 16, Golonzka teaches a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure (Claim 17 – a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure). But Golonzka does not expressly disclose the details of integrated circuit.
However, in a related art, Onogi teaches:
a gate structure ({50, 52} – Fig. 10 – [0068]) having a gate electrode (52) over a channel structure (35);
a dielectric layer (56 – [0077]) over the gate structure ({50, 52});
a gate contact via (85 – [0079]) in an opening in the dielectric layer (56), the gate contact via in (85) contact with the gate electrode (52 – via 45 – [0076]) of the gate structure ({50, 52}); and
a gate contact via extension (95 – [0078]) on the gate contact via (85), the gate contact via extension (95) above the dielectric layer (56) and extending laterally beyond the gate contact via (Fig. 10 Shows 95 extends laterally beyond 85).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of the details of the integrated circuit as taught by Onogi into Golonzka.
An ordinary artisan would have been motivated to integrate Onogi structure into Golonzka structure in the manner set forth above for, at least, for the obvious benefit of fabricating a functional integrated circuit as is well known.
Regarding claim 17, the combination of Golonzka and Onogi teaches the computing device of claim 16, further comprising: a memory coupled to the board (Golonzka – Fig. 5 teaches DRAM, ROM in the motherboard 502).
Regarding claim 18, the combination of Golonzka and Onogi teaches the computing device of claim 16, further comprising: a communication chip coupled to the board (Golonzka – Fig. 5 teaches communication chip 506 in the motherboard 502).
Regarding claim 19, the combination of Golonzka and Onogi teaches the computing device of claim 16, further comprising: a camera coupled to the board (Golonzka – [0062]).
Regarding claim 20, the combination of Golonzka and Onogi teaches the computing device of claim 16, wherein the component is a packaged integrated circuit die (Golonzka – [0064]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898