DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on February 5, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-7 and 11-20, are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Mohapatra et al. (US 2019/0198658, hereinafter Mohapatra).
Regarding claim 1, Mohapatra discloses for an integrated circuit structure, comprising that
a first sub-fin structure (sub-channel or sub-fin region 122/124/126 of S/D region 162, Fig. 1M) beneath a first stack of nanowires (channel region 128 on the left side, Fig. 1M), because the channel region 128 by Mohapatra includes a stack of nanowires 128’, as shown in Figs. 1J-1L;
a second sub-fin structure (sub-channel or sub-fin region 122/124/126 of S/D region 164, Fig. 1M) beneath a second stack of nanowires (channel region 128 on the right side, Fig. 1M);
a first epitaxial source or drain structure (S/D region 162, Fig. 1M) at an end of the first stack of nanowires (end of 128 on the left side, Fig. 1M), the first epitaxial source or drain structure (162, Fig. 1M) having a first lateral sidewall (left-sidewall of 162, see attached Fig. 1M below) having a flat vertical surface (Fig. 1M), because the S/D region 162 by Mohapatra exhibits a rectangular prism shape, therefore, left-sidewall of the S/D region is flat surface in a vertical direction, and having a second lateral sidewall opposite the first lateral sidewall (right-sidewall of 162, Fig. 1M below); Examiner notes that since Applicants do not specifically claim any particular orientation (e.g., front, left, or right) for the first and second epitaxial source or drain structures, the term “a lateral sidewall” may reasonably encompass any of the vertical side surfaces of the structure; and
a second epitaxial source or drain structure (S/D region 164, Fig. 1M) at an end of the second stack of nanowires (128 on the right side, Fig. 1M), the second epitaxial source or drain structure (164, Fig. 1M) having a first lateral sidewall (left-sidewall of 164, see attached Fig. 1M below) having a flat vertical surface (Fig. 1M), because the S/D region 164 by Mohapatra exhibits a rectangular prism shape, therefore, left-sidewall of the S/D region is flat surface in a vertical direction, and having a second lateral sidewall opposite the first lateral sidewall (right-sidewall of 164, Fig. 1M below),
the first lateral sidewall of the second epitaxial source or drain structure (left-sidewall of 164, Fig. 1M below) laterally spaced apart from and facing toward the second lateral sidewall of the first epitaxial source or drain structure (right-sidewall of 162, Fig. 1M below), because the right sidewall of the S/D 162 faces toward the left sidewall of the S/D 164.
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Regarding claim 2, Mohapatra further discloses for the integrated circuit structure of claim 1 that the second lateral sidewall of each of the first and second epitaxial source or drain structures (right-sidewall of S/D regions 162 and 164, Fig. 1M) has a flat vertical surface, because the S/D regions 162 and 164 by Mohapatra exhibit a rectangular prism shape, therefore, right-sidewall of both S/D regions is flat surface in a vertical direction.
Regarding claim 6, Mohapatra further discloses for an integrated circuit structure, comprising that
a first sub-fin structure (sub-channel or sub-fin region 122/124/126 of S/D region 162, Fig. 1M) beneath a first fin (left fin 102, Fig. 1M, 102 labeled in Fig. 1A);
a second sub-fin structure (sub-channel or sub-fin region 122/124/126 of S/D region 164, Fig. 1M) beneath a second fin (right fin 104, Fig. 1M, 104 labeled in Fig. 1A);
a first epitaxial source or drain structure (S/D region 162, Fig. 1M) at an end of the first fin (left fin 102, Fig. 1M), the first epitaxial source or drain structure (162, Fig. 1M) having a first lateral sidewall (left-sidewall of 162, see attached Fig. 1M above) having a flat vertical surface, because the S/D region 162 by Mohapatra exhibits a rectangular prism shape, therefore, left-sidewall of the S/D region is flat surface in a vertical direction, and having a second lateral sidewall opposite the first lateral sidewall (right-sidewall of 162, Fig. 1M); Examiner notes that since Applicants do not specifically claim any particular orientation (e.g., front, left, or right) for the first and second epitaxial source or drain structures, the term “a lateral sidewall” may reasonably encompass any of the vertical side surfaces of the structure; and
a second epitaxial source or drain structure (S/D region 164, Fig. 1M) at an end of the second fin (right fin 104, Fig. 1M), the second epitaxial source or drain structure (164, Fig. 1M) having a first lateral sidewall (left-sidewall of 164, Fig. 1M above) having a flat vertical surface (Fig. 1M), and having a second lateral sidewall opposite the first lateral sidewall (right-sidewall of 164, Fig. 1M above),
the first lateral sidewall of the second epitaxial source or drain structure (left-sidewall of 164, Fig. 1M above) laterally spaced apart from and facing toward the second lateral sidewall of the first epitaxial source or drain structure (right-sidewall of 162, Fig. 1M above).
Regarding claim 7, Mohapatra further discloses for the integrated circuit structure of claim 6 that the second lateral sidewall of each of the first and second epitaxial source or drain structures (right-sidewall of 162 and 164, Fig. 1M) has a flat vertical surface, because the S/D regions 162 and 164 by Mohapatra exhibit a rectangular prism shape, therefore, right-sidewall of both S/D regions is flat surface in a vertical direction.
Regarding claim 11, Mohapatra further discloses for a computing device, comprising that
a board (motherboard 1002, Fig. 3); and
a component coupled to the board (Fig. 3), the component including an integrated circuit structure (Fig. 3), comprising:
a first sub-fin structure (sub-channel or sub-fin region 122/124/126 of S/D region 162, Fig. 1M) beneath a first stack of nanowires (channel region 128 on the left side, Fig. 1M), because the channel region 128 by Mohapatra includes a stack of nanowires 128’, as shown in Figs. 1J-1L;
a second sub-fin structure (sub-channel or sub-fin region 122/124/126 of S/D region 164, Fig. 1M) beneath a second stack of nanowires (channel region 128 on the right side, Fig. 1M);
a first epitaxial source or drain structure (S/D region 162, Fig. 1M) at an end of the first stack of nanowires (end of 128 on the left side, Fig. 1M), the first epitaxial source or drain structure (162, Fig. 1M) having a first lateral sidewall (left-sidewall of 162, see attached Fig. 1M above) having a flat vertical surface, because the S/D region 162 by Mohapatra exhibits a rectangular prism shape, therefore, left-sidewall of the S/D region is flat surface in a vertical direction, and having a second lateral sidewall opposite the first lateral sidewall (right-sidewall of 162, Fig. 1M); Examiner notes that since Applicants do not specifically claim any particular orientation (e.g., front, left, or right) for the first and second epitaxial source or drain structures, the term “a lateral sidewall” may reasonably encompass any of the vertical side surfaces of the structure; and
a second epitaxial source or drain structure (S/D region 164, Fig. 1M) at an end of the second stack of nanowires (end of 128 on the right side, Fig. 1M), the second epitaxial source or drain structure (164, Fig. 1M) having a first lateral sidewall (left-sidewall of 164, Fig. 1M above) having a flat vertical surface, because the S/D region 164 by Mohapatra exhibits a rectangular prism shape, therefore, left-sidewall of the S/D region is flat surface in a vertical direction, and having a second lateral sidewall opposite the first lateral sidewall (right-sidewall of 164, Fig. 1M above),
the first lateral sidewall of the second epitaxial source or drain structure (left-sidewall of 164, Fig. 1M above) laterally spaced apart from and facing toward the second lateral sidewall of the first epitaxial source or drain structure (right-sidewall of 162, Fig. 1M above).
Regarding claim 12, Mohapatra further discloses for the computing device of claim 11 that a memory (DRAM or ROM, Fig. 3) coupled to the board (motherboard 1002, Fig. 3)
Regarding claim 13, Mohapatra further discloses for the computing device of claim 11 that a communication chip (communication chip 1006, Fig. 3) coupled to the board (1002, Fig. 3).
Regarding claim 14, Mohapatra further discloses for the computing device of claim 11 that the component is a packaged integrated circuit die, because “the processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004” (emphasis added, [0056]).
Regarding claim 15, Mohapatra further discloses for the computing device of claim 11 that the component is selected from the group consisting of a processor (processor 1004, Fig. 3), a communications chip (communication chip 1006, Fig. 3), and a digital signal processor (processor 1004, Fig. 3, “digital signal processor”, [0054]).
Regarding claim 16, Mohapatra further discloses for a computing device, comprising that
a board (motherboard 1002, Fig. 3); and
a component coupled to the board (1002, Fig. 3), the component including an integrated circuit structure (Fig. 3), comprising:
a first sub-fin structure (sub-channel or sub-fin region 122/124/126 of S/D region 162, Fig. 1M) beneath a first fin (left fin 102, Fig. 1M, 102 labeled in Fig. 1A);
a second sub-fin structure (sub-channel or sub-fin region 122/124/126 of S/D region 164, Fig. 1M) beneath a second fin (right fin 104, Fig. 1M, 104 labeled in Fig. 1A);
a first epitaxial source or drain structure (S/D region 162, Fig. 1M) at an end of the first fin (left fin 102, Fig. 1M), the first epitaxial source or drain structure (162, Fig. 1M) having a first lateral sidewall (left-sidewall of 162, see attached Fig. 1M above) having a flat vertical surface, because the S/D region 162 by Mohapatra exhibits a rectangular prism shape, therefore, left-sidewall of the S/D region is flat surface in a vertical direction, and having a second lateral sidewall opposite the first lateral sidewall (right-sidewall of 162, Fig. 1M above); Examiner notes that since Applicants do not specifically claim any particular orientation (e.g., front, left, or right) for the first and second epitaxial source or drain structures, the term “a lateral sidewall” may reasonably encompass any of the vertical side surfaces of the structure; and
a second epitaxial source or drain structure (S/D region 164, Fig. 1M) at an end of the second fin (right fin 104, Fig. 1M), the second epitaxial source or drain structure (164, Fig. 1M) having a first lateral sidewall (left-sidewall of 164, Fig. 1M above) having a flat vertical surface, because the S/D region 164 by Mohapatra exhibits a rectangular prism shape, therefore, left-sidewall of the S/D region is flat surface in a vertical direction, and having a second lateral sidewall opposite the first lateral sidewall (right-sidewall of 164, Fig. 1M),
the first lateral sidewall of the second epitaxial source or drain structure (left-sidewall of 164, Fig. 1M above) laterally spaced apart from and facing toward the second lateral sidewall of the first epitaxial source or drain structure (left-sidewall of 162, Fig. 1M above).
Regarding claim 17, claim 17 is rejected for the same reason stated in claim 12 above.
Regarding claim 18, claim 18 is rejected for the same reason stated in claim 13 above.
Regarding claim 19, claim 19 is rejected for the same reason stated in claim 14 above.
Regarding claim 20, claim 20 is rejected for the same reason stated in claim 15 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over by Mohapatra et al. (US 2019/0198658, hereinafter Mohapatra) in view of Wang et al. (“Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology”, Microelectronic Engineering, 163, 49-54, 2016; hereinafter Wang). The teachings of Mohapatra are discussed above.
Regarding claim 3, Mohapatra differs from the claimed invention by not showing that the second lateral sidewall of each of the first and second epitaxial source or drain structures has a non-flat vertical surface.
However, Wang discloses for FinFET having epitaxially grown SiGe source/drain regions that SiGe source/drain regions (Fig. 1) exhibit a rounded profile and a non-flat vertical surface along the lateral sidewall (Fig. 3); one of ordinary skill in the art would readily recognize that, during epitaxial growth processes, the surface of a lateral sidewall of a source/drain region is not perfectly flat (or planar) but exhibits surface roughness, as evidenced by the scanning electron microscope (SEM) images shown in Fig. 3 of Wang (see attached Fig. 3 of Wang below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that epitaxially grown source/drain regions may include roughened, i.e., non-flat, vertical surfaces along their lateral sidewalls, as disclosed by Wang, since a certain degree of roughness would be expected in practice due to epitaxial growth kinetics that depend on numerous parameters including a growth temperature, a cleanliness of the surface, a growth rate, a surface orientation, etc. that need to be selected, controlled and optimized.
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Regarding claim 8, claim 8 is rejected for the same reason stated in claim 3 above.
Claims 4-5 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Mohapatra et al. (US 2019/0198658, hereinafter Mohapatra) in view of Jambunathan et al. (US 2019/0355721, hereinafter Jambunathan). The teachings of Mohapatra are discussed above.
Regarding claim 4, Mohapatra differs from the claimed invention by not showing that a first trench contact structure on the first epitaxial source or drain structure, and a second trench contact structure on the second epitaxial source or drain structure, the second trench contact structure separate from the first trench contact structure.
However, Jambunathan discloses for a gate-all-around (GAA) transistor having nanowires that a first trench contact structure (leftmost S/D material 262, Fig. 2O) on the first epitaxial source or drain structure (leftmost S/D material 261, Fig. 2O), and a second trench contact structure (adjacent S/D material 262, Fig. 2O) on the second epitaxial source or drain structure (adjacent S/D material 261, Fig. 2O), because Applicants do not specifically claim where the first trench contact structure is located and/or how it looks like, the S/D material 262 is formed on the S/D material 261 in a trench between isolation structures 230 (Fig. 2O), therefore, the S/D material 262 by Jambunathan can correspond to the trench contact structure in the claimed invention, the second trench contact structure (adjacent S/D material 262, Fig. 2O) separate from the first trench contact structure (leftmost S/D material 262, Fig. 2O).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that additional S/D regions can be formed on the doped S/D regions within a trench area between isolation structures, as disclosed by Jambunathan, in order to optimize the performance of the integrated circuit.
Regarding claim 5, Mohapatra differs from the claimed invention by not showing that a trench contact structure on both the first epitaxial source or drain structure and the second epitaxial source or drain structure.
However, Jambunathan further discloses that a trench contact structure (S/D material 262, Fig. 2K) on both the first epitaxial source or drain structure (leftmost 261, Fig. 2K) and the second epitaxial source or drain structure (adjacent 261, Fig. 2K).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that additional S/D regions can be formed and extended on the plurality of doped S/D regions within a trench area between isolation structures, as disclosed by Jambunathan, in order to optimize the performance of the integrated circuit.
Regarding claim 9, claim 9 is rejected for the same reason stated in claim 4 above.
Regarding claim 10, claim 10 is rejected for the same reason stated in claim 5 above.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 6, 11 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815