DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/06/2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nii (U.S. PG Pub No US2018/0068708A1) (of record).
Regarding claim 1, Nii teaches a semiconductor structure (1000) fig. 13 [0211] comprises:
an active region pattern (comprising PW, NW regions bordering FL) fig. 13 [0113, 0096];
a first type of grid patterns (comprising FL302-310 in fig. 13 and M202 in fig. 14) figs. 13, 14 [0096-0099, 0132, 0224] overlapping with the active region pattern (comprising PW0 region) and (collectively) extending along a first direction (DR1) [see annotated fig. 13 below]; and
a metal layer pattern (upper metal interconnection layer(s) comprising MP’s) fig. 13 [0211-0219] extending (in-part) along the first direction (DR1) (comprising vertically-extending portions of MP2, MP3) [see annotated fig. 13 below];
wherein the metal layer pattern (upper metal interconnection layer(s) comprising MP’s) is in contact with the active region pattern (comprising PW0 bordering FL) arranged on both (left/right) sides of the first type of grid patterns (FL302-310) through a contact hole pattern (CT’s comprising CT6, CT8, CT10, CT12…) fig. 13 [0211, 0096-0099;
wherein the active region pattern (comprising PW, NW regions bordering FL) fig. 13 [0113, 0096] comprises a first active region pattern (PW0) [0113, 0096], the first type of grid patterns (comprising FL302-310) fig. 13 [0096] comprises a first grid pattern (FL302-310), and the metal layer pattern (upper metal interconnection layer(s) comprising MP’s) annotated fig. 13 below [0211-0219] comprises:
a first type of metal line patterns (MP1-2) [0132] comprising a first metal line pattern (MP1) and a second metal line pattern (MP2) which are entirely spaced in a second direction (DR2) and both of strip-shaped (rectangular-shaped) configuration, wherein the first metal line pattern (MP1) is in contact with the first active region pattern (PW0 bordering FL302-310) arranged on (supported by) a first (top) side of the first grid pattern (FL302-310, M202) through a first contact hole pattern (CT6) [0096-0099, 0211]; and
a second type of metal line patterns (MP3-4) [0132] comprising a third metal line pattern (MP3) and a fourth metal line pattern (MP4) which are entirely spaced in the second direction (DR2) and both of strip-shaped (rectangular-shaped) configuration, wherein the third metal line pattern (MP3) is arranged (in the space) between (portions of) the first metal line pattern (MP1) and the second metal line pattern (MP2) (see annotated fig. 13 below), the fourth metal line pattern (MP4) is arranged on a (lower) side of the second metal line pattern away from the first metal line pattern (MP2), the fourth metal line pattern (MP4) is in contact with the first active region pattern (PW0 bordering FL302-310) arranged on (supported by) a second (bottom) side of the first grid pattern (FL302-310) through a second contact hole pattern (CT12) [0099], the second (bottom) side is opposite to the first (top) side (see annotated fig. 13 of Nii below);
wherein in the second direction (DR2), a width (W2) of the second metal line pattern (MP2) [0211-0219] is smaller than a width (W1) of the first metal line pattern (MP1), and a width (W3) of the third metal line pattern (MP3) is smaller than a width (W4) of the fourth metal line pattern (MP4) (see annotated fig. 13 of Nii below), and a width of the first grid pattern (comprising FL302-310 width in DR2) [0096] is (clearly) smaller than a distance (in DR1) between the first metal line pattern (MP1) and the fourth metal line pattern (MP4) (see annotated fig. 13 of Nii below) (MP1, MP4 versus MP2, MP3 are different shapes with distinct sidewall positions and identifiable widths).
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Annotated fig. 13 of Nii
Regarding claim 5, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 1. Nii also teaches wherein the second metal line pattern (MP2) and the third metal line pattern (MP3) are at least partially overlapped with the first grid pattern (comprising M202) fig. 14 [0096-0099, 0132, 0224] (see annotated fig. 13 of Nii above relative to annotated fig. 14 of Nii below).
[AltContent: arrow][AltContent: textbox (MP3-outline )][AltContent: arrow][AltContent: textbox (MP2-outline )]
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Annotated fig. 14 of Nii designating outlines of MP2, MP3 relative to M202
Regarding claim 6, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 1. Nii also teaches wherein the first metal line pattern (MP1) is in contact with the first active region pattern (PW0 bordering FL302-310) annotated fig. 13 above [0113, 0096] arranged on (supported by) the first (top) side of the first grid pattern (FL302-310) through at least two first contact hole patterns (CT6, CT8 in electrical contact with both MP1 and FL302-310) fig. 13 [0096-0099, 0221] arranged in parallel, and the fourth metal line pattern (MP4) is in contact with the first active region pattern (PW0 bordering FL302) on (supported by) the second (bottom) side of the first grid pattern (FL302-310) through at least two second contact hole patterns (CT12, CT10 in electrical contact with both MP1 and FL302-310) arranged in parallel.
Regarding claim 7, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 1. Nii also teaches wherein the first type of grid patterns (FL and M202) [0113, 0132] further comprises a second grid pattern (FL312, FL314, FL316) fig. 13 [0100-0101] spaced from the first grid pattern (FL302-310 and M202) in the second direction (DR2) (see annotated fig. 13 above), the second grid pattern (FL312, FL314, FL316) fig. 13 [0100-0101] is overlapped with the first active region pattern (comprising PW0 and NW0) fig. 13 [0113, 0096] and in parallel with the first grid pattern (FL302-310, M202) (FL’s, M202extend in DR1), the first type of metal line patterns further comprises a fifth metal line pattern (gate material MP5) annotated fig. 13 above [0092, 0214] (gate may be composed of metal [0092]) and a sixth metal line pattern (gate material MP6) annotated fig. 13 above [0092, 0214] (gate may be composed of metal [0092]) which are spaced in the second direction (DR2) (right sidewalls of MP5, MP6 spaced apart in DR2) (see annotated fig. 13 above), wherein the sixth metal line pattern (MP6) is connected to the first active region pattern (comprising PW0 and NW0 bordering FL) on a (top) side of the second grid pattern (FL312, FL314, FL316) fig. 13 [0100-0101] away from the (bottom side of) first grid pattern (FL302-310) through a third contact hole pattern (CT14) fig. 13 [0099]; and
the second type of metal line patterns further comprises a seventh metal line pattern (MP7 of metal interconnection layers) [0211-0219] arranged (vertically) between the fifth metal line pattern (MP5) and the sixth metal line pattern (MP6).
Regarding claim 8, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 7. Nii also teaches wherein in the second direction (DR2), a width of the second grid pattern (FL312, FL314, FL316) fig. 13 [0100-0101] is (clearly) smaller than a distance between the fourth metal line pattern (MP4) and the seventh metal line pattern (MP7).
Regarding claim 9, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 7. Nii also teaches wherein the fifth metal line pattern (MP5) and the seventh metal line pattern (MP7) are at least partially overlapped with the second grid pattern (FL312, FL314, FL316) annotated fig. 13 above [0100-0101].
Regarding claim 10, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 1. Nii also teaches further comprising a second type of grid patterns (FL312, FL314, FL316) fig. 13 [0100-0101], wherein the second type of grid patterns (FL312, FL314, FL316) is overlapped with the active region pattern (comprising PW0 and NW0) fig. 13 [0113, 0096] and extends along a second direction (DR2), and the metal layer pattern (upper metal interconnection layer(s) comprising MP’s 5-7) fig. 13 [0211-0219] is in contact with the active region pattern (PW0, NW0) arranged on both sides (upper/lower sides) of the second type of grid patterns (FL312-316) through the contact hole pattern (CT’s comprising CT6, CT8, CT10, CT12…CT22) fig. 13 [0211, 0096-0101] (see annotated fig. 13 above).
Regarding claim 11, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 10. Nii also teaches wherein a width of the second type of grid patterns (comprising FL312) in the first (vertical) direction is smaller than a width of the first type of grid patterns (comprising FL 302) in the second direction (FL302 region horizontally wider than vertical length of F312; see annotated fig. 13 above).
Regarding claim 12, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 11. Nii also teaches wherein the active region pattern (comprising PW, NW regions bordering FL) fig. 13 [0113, 0096] comprises a second active region pattern (comprising PW1, NW1, PW2 bordering respective FLs) fig. 13 [0113, 0213], the second type of grid patterns comprises a third grid pattern (FL318-326) annotated fig. 13 [0102-0105], a fourth grid pattern (FL328-336) fig. 13 [0106-0109], a fifth grid pattern (FL 360-364) fig. 13[0214-0216] and a sixth grid pattern (FL366-374) fig. 13 [0217-0219], wherein the third grid pattern (FL318-326), the fourth grid pattern (FL328-336), the fifth grid pattern (FL 360-364) and the sixth grid pattern (FL366-374) are (individually) spaced in the first direction (DR1) and all (individually) extend along the second direction (DR2), and are overlapped with the second active region pattern (PW1, NW1, PW2 bordering respective FLs), the fourth grid pattern (FL328-336) and the fifth grid pattern (FL 360-364) are arranged in parallel (in DR2), and the third grid pattern (FL318-326) and the sixth grid pattern (FL366-374) are arranged in parallel (in DR2);
at least two fourth contact hole patterns (CT28, CT30, CT32) fig. 13 [0122-0125] arranged in parallel are arranged on a side of the third grid pattern (FL318-326) away from the fourth grid pattern (FL328-336) and overlapped with the second active region pattern (comprising PW1, NW1, PW2);
at least two fifth contact hole patterns (CT40, CT42) fig. 13 [0126-0128] arranged in parallel are arranged (diagonally) between the fourth grid pattern (FL328-336) and the fifth grid pattern (FL 360-364), and overlapped with the second active region pattern (comprising PW1, NW1, PW2);
at least two sixth contact hole patterns (CT74-CT82) fig. 13 [0218] arranged in parallel are arranged on a side of the sixth grid pattern (FL366-374) away from the fifth grid pattern (FL 360-364), and overlapped with the second active region pattern (comprising PW1, NW1, PW2); and
the metal layer pattern (upper metal interconnection layer(s) comprising MP’s) fig. 13 [0211-0219] is in contact with the second active region pattern (comprising PW1, NW1, PW2) through the fourth contact hole pattern, the fifth contact hole pattern and the sixth contact hole pattern (CT28-82) (connected through CT28-82 and respective FL’s).
Regarding claim 13, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 1. Nii also teaches wherein the active region pattern (comprising PW, NW regions bordering FL) further comprises a third active region pattern (comprising PW1, NW1, PW2 bordering respective FLs) fig. 13 [0113, 0213];
the first type of grid patterns comprises a seventh grid pattern (FL318-326) annotated fig. 13-II below [0102-0105] and an eighth grid pattern (FL 360-364) fig. 13 [0214-0216], the seventh grid pattern (FL318-326) and the eighth grid pattern (FL 360-364) are spaced in a second (horizontal) direction and both extend (collectively) along the first (vertical) direction and are overlapped with the third active region pattern (comprising PW1, NW1, PW2 bordering respective FLs);
the metal layer pattern (upper metal interconnection layer(s) comprising MP’s) annotated fig. 13-II below [0211-0219] comprises:
a first type of metal line patterns comprising an eighth metal line pattern (MP8), a ninth metal line pattern (MP9) and a tenth metal line pattern (MP10) which are spaced in the second direction (DR2) [see annotated fig. 13 below] wherein the ninth metal line pattern (MP9) is in contact with the third active region pattern (PW1, NW1, PW2) between the seventh grid pattern (FL318-326) and the eighth grid pattern (FL 360-364) through a tenth contact hole pattern (CT36) [0107] (see annotated fig. 13-II below); and
a second type of metal line patterns comprising an eleventh metal line pattern (MP11), a twelfth metal line pattern (MP12), a thirteenth metal line pattern (MP13) and a fourteenth metal line pattern (MP13) which are (at least partially) spaced in the second direction (DR2), wherein the eighth metal line pattern (MP8) is arranged (horizontally) between the eleventh metal line pattern (MP11) and the twelfth metal line pattern (MP12), the ninth metal line pattern (MP9) is arranged (diagonally) between the twelfth metal line pattern (MP12) and the thirteenth metal line pattern (MP13), the tenth metal line pattern (MP10) is arranged (diagonally) between the thirteenth metal line pattern (MP13) and the fourteenth metal line pattern (MP14), the eleventh metal line pattern (MP11) is in contact with the third active region pattern on (above) a (left) side of the seventh grid pattern (FL318-326) away from the (left side of) eighth grid pattern (FL 360-364) through a ninth contact hole pattern (CT24) annotated fig. 13-II [0102], the fourteenth metal line pattern (MP14) is in contact with the third active region pattern on (above) a side (left) of the eighth grid pattern (FL 360-364) away from the (right side of ) seventh grid pattern (FL318-326) through an eleventh contact hole pattern (CT38) annotated fig. 13-II below [0109].
[AltContent: textbox (DR2)][AltContent: arrow][AltContent: arrow][AltContent: textbox (DR1)][AltContent: arrow][AltContent: arrow][AltContent: textbox (MP11)][AltContent: textbox (MP10)][AltContent: arrow][AltContent: textbox (MP12)][AltContent: textbox (MP13)][AltContent: arrow][AltContent: arrow][AltContent: textbox (MP14)][AltContent: textbox (MP9)][AltContent: arrow][AltContent: textbox (MP8)][AltContent: arrow]
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Annotated fig. 13-II of Nii
Regarding claim 14, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 13. Nii also teaches wherein in the second direction (DR2), a width of the seventh grid pattern (FL318-326) annotated fig. 13-II above [0102-0105] is (clearly) smaller than a distance between the ninth metal line pattern (MP9) and the eleventh metal line pattern (MP11), and a width of the eighth grid pattern (FL 360-364) annotated fig. 13-II above [0102-0105] is smaller than a distance between the ninth metal line pattern (MP9) and the fourteenth metal line pattern (MP14).
Regarding claim 15, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 1. Nii also teaches wherein the active region pattern comprises a fourth active region pattern (comprising NW0, PW1, NW1 bordering respective FLs) fig. 13 [0113, 0213], the first type of grid patterns comprises a ninth grid pattern (FL312- FL316) fig. 13 [0100-0101], a tenth grid pattern (FL318-326) fig. 13 [0102-0105], an eleventh grid pattern (FL328-336) fig. 13 [0106-0109] and a twelfth grid pattern (FL 360-364) fig. 13 [0214-0216] arranged in parallel, the ninth grid pattern (FL312- FL316), the tenth grid pattern (FL318-326), the eleventh grid pattern (FL328-336) and the twelfth grid pattern (FL 360-364) are spaced in a second (horizontal) direction and all (collectively) extend along the first (vertical) direction, and are overlapped with the fourth active region pattern (comprising NW0, PW1, NW1 bordering respective FLs) fig. 13 [0113, 0213], and the metal layer pattern (upper metal interconnection layer(s) comprising MP’s) fig. 13 [0211-0219] is in (electrical) contact with the fourth active region pattern (comprising NW0, PW1, NW1 bordering respective FLs) on both (left/right) sides of the ninth grid pattern (FL312- FL316), the tenth grid pattern (FL318-326), the eleventh grid pattern (FL328-336) and the twelfth grid pattern (FL 360-364) through the contact hole pattern (CT’s comprising CT18- CT68…) fig. 13 [0211].
Regarding claim 16, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 15. Nii also teaches wherein the active region pattern comprises a fifth active region pattern (comprising PW2 bordering respective FLs) fig. 13 [0113, 0213], a second type of grid patterns (gate material) [0214-0216] comprises a thirteenth grid pattern (G13), a fourteenth grid pattern (G14), a fifteenth grid pattern (G15) and a sixteenth grid pattern (G16) arranged in parallel (see annotated fig. 13-III below), the thirteenth grid pattern (G13), the fourteenth grid pattern (G14), the fifteenth grid pattern (G15) and the sixteenth grid pattern (G16) are spaced in the first (vertical) direction and all extend along the second (horizontal) direction, and are overlapped with the fifth active region pattern (comprising PW2), and the metal layer pattern (upper metal interconnection layer(s) comprising MP’s) fig. 13 [0211-0219] is in (electrical) contact with the fifth active region pattern on both sides of the thirteenth grid pattern (G13), the fourteenth grid pattern (G14), the fifteenth grid pattern (G15) and the sixteenth grid pattern (G16) through the contact hole pattern (CT’s comprising CT74- CT82) fig. 13 [0211] (see annotated fig. 13-III below).
[AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (G16)][AltContent: textbox (G15)][AltContent: textbox (G14)][AltContent: textbox (G13)]
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Annotated fig. 13-III of Nii
Regarding claim 17, Nii teaches the semiconductor structure (1000) fig. 13 [0211] of claim 13. Nii also teaches wherein the active region pattern further comprises a fifth active region pattern (comprising PW2 bordering respective FLs) fig. 13 [0113, 0213], a second type of grid patterns comprises a seventeenth grid pattern (“G15”) annotated fig. 13-III above [0214-0216] extending along the second (horizontal) direction and overlapping with the fifth active region pattern (comprising PW2), and the metal layer pattern (upper metal interconnection layer(s) comprising MP’s) fig. 13 [0211-0219] is in contact with the fifth active region pattern (PW2) arranged on one (top) side of the seventeenth grid pattern through the contact hole pattern (CT’s comprising CT72) fig. 13 [0211, 0218].
Regarding claim 18, Nii teaches a memory [0223] comprising the semiconductor structure (1000) fig. 13 [0211] of claim 1.
Response to Arguments
Applicant's arguments filed 02/06/2026 have been fully considered but they are rendered largely moot by a reinterpretation of the second (MP2) and third (MP3) metal patterns of Nii, which are entirely spaced apart from the first (MP1) and fourth (MP4) metal patterns, respectively, in both the first (DR1) and second (DR2) directions (see annotated fig. 13 in rejection of claim 1 above). With this reinterpretation, each of the first-fourth metal patterns (MP1-MP4) possess a rectangular-strip shape. Further, the “first type of grid patterns” have been reinterpreted to further comprise grid pattern M202 [see fig. 14, 0132, 0224] of Nii, such that “the second metal line pattern (MP2) and the third metal line pattern (MP3) are at least partially overlapped with the first grid pattern (comprising M202) fig. 14 [0096-0099, 0132, 0224] – see annotated fig. 14 in rejection of claim 5 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they all feature active semiconductor device layouts with a plurality of metal and grid patterns.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 03/13/2026
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