Prosecution Insights
Last updated: May 29, 2026
Application No. 17/955,681

PACKAGE STRUCTURE, PACKAGING METHOD AND SEMICONDUCTOR DEVICE

Final Rejection §103§112
Filed
Sep 29, 2022
Priority
Jun 01, 2022 — CN 202210621408.5 +1 more
Examiner
GOODWIN, DAVID J
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Changxin Memory Technologies Inc.
OA Round
3 (Final)
67%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
544 granted / 807 resolved
-0.6% vs TC avg
Strong +16% interview lift
Without
With
+16.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
36 currently pending
Career history
879
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
82.6%
+42.6% vs TC avg
§102
3.1%
-36.9% vs TC avg
§112
10.4%
-29.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 807 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Status Previous rejection: claims 1 through 5 withdrawn, claims 6 through 12 rejected. Present rejection: claims 1 through 5 are withdrawn claims 6 through 12 are rejected Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6 through 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites “wherein the fourth pad is formed by removing part of a first pad” in line 8. The applicant is claiming a product rather than a process of making a product. Further, where a pad is removed it is not part of the final product. Reciting limitations suggesting that there are four pads result in an ambiguity as to how many pads there are. The claim will be understood to comprise three pads: a first pad, a second pad, and a third pad. The applicant is advised to only claim elements of the product without ambiguous implications. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s) or addressed using the appropriate case law. Claim(s) 6 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2018/0240736) in view of Ko (US 2012/0043663) Regarding claim 6. Liu teaches: a package structure, comprising: an isolation layer (fig 2b:108; [para 0033]) with a via hole (fig 2b:O2; [para 0038]), the isolation layer (fig 2b:108; [para 0033]) closely covering a surface of an layer (fig 2b:102; [para 0033]), the via hole (fig 2b:O2; [para 0038]) exposing part of the layer (fig 2b:102; [para 0033]), and the layer (fig 2b:102; [para 0033]),being disposed on a surface of a semiconductor functional structure (fig 2b:100; [para 0034]); a fourth pad (fig 2b:102a; [para 0040]) consisting entirely of the layer (fig 2b:102; [para 0033]), exposed by the isolation layer (fig 2b:108; [para 0033]), an area (fig 2b:A; [para 0042]) of the fourth pad (fig 2b:102a; [para 0042]) being less than a cross-sectional area of the via hole (fig 2b:O2; [para 0040]), and the cross-sectional area of the via hole (fig 2b:O2; [para 0040]) being set based on requirements of a first type test (the first type of test being contact with a probe and the requirements for the first type of test being a pad surface being exposed for contact with a probe ([para 0040,0042]); a redistribution layer (fig 2b:113; [para 0031]) covering the isolation layer (fig 2b:108; [para 0033]) and being electrically connected with the fourth pad (fig 2b:102a; [para 0031]); and a first insulating layer (fig 2b:112; [para 0033]) covering and exposing part of the redistribution layer (fig 2b:113; [para 0031]), wherein the exposed parts (fig 2a,2b:111,109; [para 0034]) of the redistribution layer (fig 2b:113; [para 0031]) comprise a second pad (fig 2a,2b:111; [para 0034]) and a third pad (2a,2b:109; [para 0034]), PNG media_image1.png 358 650 media_image1.png Greyscale The limitation must distinguish from the prior art in terms of structure rather than function (ie testing running speed, functional interactions, and the relative performance of the first and second tests), In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See also In re Swinehart, 439 F.2d210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971). Claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danly, 263 F. 2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F. 2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). Further, note that a “product by process” claim is directed to the product per se, no matter how actually made (ie “wherein the fourth pad is formed by removing part of a first pad, which is completely exposed by the via hole of the isolation layer, the area of the first pad is determined by the cross-sectional area of the via hole, and the area of the first pad is equal to the cross-sectional area of the via hole”, how the fourth pad is formed and the preceding properties thereof). See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and related case law cited therein which make it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe, Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington. 411 F2d 1345, 1348, 162 USPQ 145, 147, (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir 1935). Note that Applicant bears the burden of proof in such cases as the above case law makes clear. Liu does not state that the layer provided on the surface of the semiconductor structure comprises a conductive interconnect layer. Ko teaches: an underlying layer comprising an isolation layer (fig 2:140; [para 0031]) with a via (fig 2:306; [para 0032]) hole, the isolation layer (fig 2:140; [para 0031]) covering a surface of an interconnecting layer (fig 2:304; [para 0032]), the via (fig 2:306; [para 0032]) hole exposing part of the interconnecting layer (fig 2:304; [para 0032]), and the interconnecting layer (fig 2:304; [para 0032]) being disposed on a surface of a semiconductor functional structure (fig 2:101; [para 0029]), and a pad consisting of the part of the interconnecting layer (fig 2:304; [para 0032]) exposed by the isolation layer (fig 2:140; [para 0032]). PNG media_image2.png 489 616 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the pad portion exposed by the via hole is a portion of an interconnecting layer in order to electrically connect the metal pad to the semiconductor device (Liu paragraph 35) and thereby the voltage applied to the pad can be conducted through to other circuitry Regarding claim 11. Liu in view of Ko teaches the package structure of claim 6 Liu further teaches: a semiconductor device comprising the package structure ([para 0033]). Claim(s) 7, 8, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2018/0240736) in view of Ko (US 2012/0043663) as applied to claim 6 and further in view of Park (US 2009/0283903) Regarding claim 7. Liu in view of Ko teaches the package structure according to claim 6 above, further. Liu in view of Ko does not teach a pillar between the pad and the redistribution layer. Park teaches: a conductive pillar (fig 13:118; [para 0057]) located between the fourth pad (fig 13:115; [para 0056]) and the redistribution layer (fig 9,13:140; [para 0051]), and the redistribution layer (fig 9,13:140; [para 0051]) and the interconnecting layer (fig 15:120,115; [para 0056]) being electrically connected by the conductive pillar (fig 13,15:118; [para 0057]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a conductive pillar in order to limit cracking and electromigration related to high current density ([para 0009,0010]). Regarding claim 8. Liu in view of Ko in view of Park teaches the package structure of claim 7, Park teaches: a number of the conductive pillar (fig 13:118; [para 0057]) is one or more (fig 13; [para 0057]). Regarding claim 10. Liu in view of Ko in view of Park teaches the structure of claim 7. Liu teaches: the second pad (fig 2a,2b:111; [para 0031]) is located at a side close to an edge of the semiconductor functional structure (fig 2a,2b:100; [para 0031]); and the third pad (fig 2a:109; [para 0031]) is located at a side away from the edge of the semiconductor functional structure (fig 2a,2b:100; [para 0031]). PNG media_image3.png 275 693 media_image3.png Greyscale Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2018/0240736) in view of Ko (US 2012/0043663) as applied to claim 6 and further in view of Kuan (US 7901956) Regarding claim 9. Liu in view of Ko teaches elements the package structure according to claim 6 above. Liu teaches: a second insulating layer (fig 2b:112; [para 0033]), a groove surrounded by the redistribution layer (fig 2b:113; [para 0034]), wherein a hardness of a material (benzocyclobutene (BCB); [para 0040]) of the second insulating layer (fig 2b:112; [para 0040]) is less than a hardness of a material (palladium, nickel) of the redistribution layer (fig 2b:113; [para 0039]). Liu in view of Ko does not teach the second insulating layer is located in the groove. Kuan teaches: a second insulating layer (fig 3f:40; [column 5 lines 30-35]), located in a groove surrounded by the redistribution layer (fig 3f:36; [column 5 lines 30-35]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the second insulating layer in the groove of the redistribution layer in order provide a location for probe testing of the device without damaging the solder ball (column 1 lines 48-55) and able to test the extension of the redistribution layer (column 2 lines 45-57) Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2018/0240736) in view of Ko (US 2012/0043663) as applied to claim 11 and further in view of Camacho (US 2012/0299191) Regarding claim 12. Liu in view of Ko teaches the semiconductor device of claim 11. Liu in view of Ko does not teach stacked die. Camacho teaches: a substrate (fig 7:212; [para 0069]); and a plurality of stacked dies (fig 7:140,156,176; [para 0069]), each die comprising the semiconductor functional structure (fig 7:124,146,166; [para 0069]) and the package structure (fig 7; [para 0069]) located on the semiconductor functional structure (fig 7:124,146,166; [para 0069]), wherein each die is electrically connected to the substrate (fig 7:212; [para 0069]) by a lead (fig 7:160,144; [para 0069] on the third pad (fig 7:132,152,172; [para 0069]) of the package structure (fig 7; [para 0069]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to stack and connect a plurality of die on a substrate in order to reduce the footprint of the structure (paragraph 7,8). Response to Arguments Applicant's arguments filed 2/4/26 have been fully considered but they are not persuasive. The applicant argues that the amendment to claim 6 resolves the ambiguity. However, it remains unclear whether there are 3 pads or four pads. The claim recites that a fourth pad is formed by removing a portion of a first pad. It is therefore unclear whether the first pad remains, is the fourth pad the same structure as the first pad, or if the fourth pad is a distinct structure from the first pad. The applicant is advised to consider which structure at a specific point in time is intended to be claimed. The applicant argues that the amendments to the claim distinguish the claim from the applied prior art. Specifically, the applicant argues that the fourth pad is formed by removing portions of a first pad, and the first pad had particular properties. However, the amendment details the process by which the fourth pad is formed and describes properties (area) of the first pad before the fourth pad was formed therefrom. A “product by process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and related case law cited therein which make it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe, Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington. 411 F2d 1345, 1348, 162 USPQ 145, 147, (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir 1935). Note that Applicant bears the burden of proof in such cases as the above case law makes clear. The applicant argues that isolation “tightly and closely” covers the interconnecting layers, and therefore there is no gap. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “no gap”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Further, the applicant will note Ko teaches there is no gap between the isolation layer (140) and the interconnecting layer (304) outside of the pad region. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.J.G/Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 27, 2026
Read full office action

Prosecution Timeline

Sep 29, 2022
Application Filed
Jun 20, 2025
Non-Final Rejection mailed — §103, §112
Sep 10, 2025
Response Filed
Nov 05, 2025
Non-Final Rejection mailed — §103, §112
Feb 04, 2026
Response Filed
Apr 29, 2026
Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12635278
IMAGING DEVICE, METHOD OF MANUFACTURING IMAGING DEVICE, AND ELECTRONIC APPARATUS
4y 0m to grant Granted May 19, 2026
Patent 12628463
METHODS AND SYSTEM OF ENHANCED NEAR-INFRARED LIGHT ABSORPTION OF IMAGING SYSTEMS USING METASURFACES AND NANOSTRUCTURES
4y 1m to grant Granted May 12, 2026
Patent 12622230
TEST STRUCTURE AND METHOD FOR FORMING THE SAME, AND SEMICONDUCTOR MEMORY
3y 7m to grant Granted May 05, 2026
Patent 12615843
METHOD FOR PREPARING DISPLAY SUBSTRATE AND DISPLAY SUBSTRATE
3y 4m to grant Granted Apr 28, 2026
Patent 12575453
SEMICONDUCTOR DEVICE
3y 3m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

4-5
Expected OA Rounds
67%
Grant Probability
84%
With Interview (+16.3%)
3y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 807 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month