DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8 & 11-18 in the reply filed on 12/29/2025 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claim limitations must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claims 1 & 16:
a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer; and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment (note bolded portions).
Claims 2 & 17:
the third conducting line segment in the second portion of the interconnect line electrically connects the first conducting line segment and the second conducting line segment in the first portion of the interconnect line.
Claim 8:
wherein at least one of the first via and the second via are coupled to at least a portion of an active device structure.
The Examiner suggests that applicants map said claim features to a specific drawing to help resolve the ambiguity.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: There appears to be reference numerals in the specification that do not have corresponding description in the drawings (e.g. Vx, Mx, V(x-1) and more).
Appropriate correction/clarification is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 & 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 & 16 recite the limitation “a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer; and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment (note bolded portions). The limitations raises ambiguity as it is unclear what specific structural features (e.g. in Fig. 1A, Fig. 2A and/or Fig. 3A) the claim limitations are referring to. The Examiner suggests that applicants map said claim features to a specific drawing to help resolve the ambiguity.
Claims 2-8 and 17-18 are rejected for being dependent on claims 1 & 16.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
As best understood, claims 1-8 & 11-18 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by YEW et al. (US Pub. 2023/0069830).
Regarding claim 1, YEW teaches a semiconductor structure comprising:
a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer (portion of dielectric layer 130, see Fig. 1B below); and
a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment (see Fig. 1B below and note the annotations).
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Regarding claim 2, YEW teaches the semiconductor structure of claim 1, wherein the third conducting line segment in the second portion of the interconnect line electrically connects the first conducting line segment and the second conducting line segment in the first portion of the interconnect line (Fig. 1B above).
Regarding claim 3, YEW teaches the semiconductor structure of claim 1, wherein the first portion of the interconnect line and the second portion of the interconnect line are part of a same interconnect level of an interconnect structure (Fig. 1B above).
Regarding claim 4, YEW teaches the semiconductor structure of claim 1, wherein the interconnect line provides at least a portion of a front side power distribution network.
Regarding claim 5, YEW teaches the semiconductor structure of claim 1, wherein the interconnect line provides at least a portion of a back side power distribution network (Fig. 1B).
Regarding claim 6, YEW teaches the semiconductor structure of claim 1, wherein the first conducting line segment is connected to a first via and the second conducting line segment is connected to a second via (see Fig. 1B).
Regarding claim 7, YEW teaches the semiconductor structure of claim 6, wherein at least one of the first via and the second via are coupled to at least one additional interconnect line 120 (Fig, 1B and Fig. 2A).
Regarding claim 8, YEW teaches the semiconductor structure of claim 6, wherein at least one of the first via and the second via are coupled to at least a portion of an active device structure (it is understood that the first and the second vias are connected to an active device in YEW’s semiconductor device.
Regarding claim 11, YEW teaches an interconnect structure comprising:
a stacked interconnect line, the stacked interconnect line comprising a first portion comprising two or more conducting line segments separated by an isolating layer (portion of dielectric layer 136) and a second portion vertically stacked over the first portion (see Fig. 1B below); and
one or more vias connecting the stacked interconnect line with an additional structure (see Fig. 1B below).
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Regarding claim 12, YEW teaches the interconnect structure of claim 11, wherein the additional structure 120 comprises an additional interconnect line (Fig. 1B).
Regarding claim 13, YEW teaches the interconnect structure of claim 12, wherein the stacked interconnect line is in a first line level of the interconnect structure and the additional interconnect line is in a second line level of the interconnect structure (Fig. 1B).
Regarding claim 14, YEW teaches the interconnect structure of claim 11, wherein the additional structure comprises an active device structure (Para [0014, wherein YEW teaches the presence of substrate comprising active device).
Regarding claim 15, YEW teaches the interconnect structure of claim 14, wherein the active device structure comprises one or more transistors (Para [0014]).
Regarding claim 16, YEW teaches an integrated circuit comprising:
a semiconductor structure comprising:
a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer (portion of 136, see annotations in Fig. 1B below & Fig. 2C) ; and
a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment (see Fig. 1B below).
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Regarding claim 17, YEW teaches the integrated circuit of claim 16, wherein the third conducting line segment in the second portion of the interconnect line electrically connects the first conducting line segment and the second conducting line segment in the first portion of the interconnect line (see Fig. 1B above).
Regarding claim 18, YEW teaches the integrated circuit of claim 16, wherein the first portion of the interconnect line and the second portion of the interconnect line are part of a same interconnect level of an interconnect structure (Fig. 1B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818