DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDSs) submitted on 10/28/2022 (two submitted), 9/22/2023, 10/19/2023, 7/2/2025, 7/24/2025, and 2/13/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restriction
It has been acknowledged that the applicant has elected without traverse Invention Group I by withdrawing claims 9-17 (Group I) and claims 18-25 (Group III) per the response dated on 1/20/2026. Currently claims 1-8 are present for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “TECHNOLOGIES FOR PEROVSKITE RIBBON TRANSISTORS WITH FERROELECTRIC GATE DIELECTRIC”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yin (CN 113178491 A).
Regarding claim 1, Yin teaches a device (negative capacitance field effect transistor (NC-FET, Figs. 11-12, [0058]) comprising:
a field effect transistor (FET) (negative capacitance field effect transistor (NC-FET, Figs. 11-12) comprising:
a plurality of fins (nanosheets 202, Figs. 11-12, [0047]);
a plurality of spacers (support structures 201, Figs. 11-12, [0047]), wherein the plurality of spacers (support structures 201, Figs. 11-12) are interleaved with the plurality of fins nanosheets 202, Figs. 11-12;
a dielectric layer (high interface oxide layer 104 and ferroelectric layer 110, Fig. 12, [0063]: “The high-interface oxide layer can be SiO2; the ferroelectric layer material is SiHfZrO2, HfO or HfAIO.”, which are all dielectric materials) adjacent the plurality of fins (nanosheets 202, Fig. 12) and the plurality of spacers (support structures 201, Fig. 12); and
a gate (metal gate 105, Fig. 12, [0056]) adjacent the dielectric layer (ferroelectric layer 110, Fig. 12).
Regarding claim 6, Yin teaches the device of claim 1, wherein the dielectric layer (high interface oxide layer 104 and ferroelectric layer 110, Fig. 12) comprises a ferroelectric layer (ferroelectric layer 110, [0063]: “the ferroelectric layer material is SiHfZrO2, HfO or HfAIO” which are all ferroelectric materials).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yin (CN 113178491 A) as applied to claims 1 and 6 above, and further in view of Cheng (Cheng et al., Electron transport of perovskite oxide BaSnO3 on (110) DyScO3 substrate with channel-recess for ferroelectric field effect transistors. Appl. Phys. Lett. 25 January 2021; 118 (4): 042105. https://doi.org/10.1063/5.0022550).
Regarding claim 2, while Yin teaches the device of claim 1,
Yin does not teach that the plurality of fins comprise lanthanum, barium, tin, and oxygen.
Cheng, on the other hand, teaches a HFO2/BSO (BaSnO3) FeFET (ferroelectric field effect transistor) (Fig. 2a; page 5, col. 1, para. 2) wherein the channel material (analogous to the fins of Yin) is lanthanum (La) doped BaSnO3 (Fig. 2a), and therefore comprises lanthanum, barium, tin, and oxygen.
A person of ordinary skill in the art before the effective filing date of the claimed invention would already know that using La doped BaSnO3 as the channel material in negative capacitance transistors (NCFET, page 28) such as the one taught by Yin has advantages as evidenced by Shoron (Omor Faruk Shoron, “Novel Channel Materials for Field-Effect Devices: Barium Stannate and Cadmium Arsenide”, Thesis Dissertation, 2021), which teaches novel channel materials for negative capacitance field-effect devices (Shoron: Abstract, page X). Shoron discloses that one of the fundamental challenges of NCFETs is the proper integration of the ferroelectric layer on a semiconducting channel (page 31). Also, the semiconducting channel's carrier density must match the ferroelectric layer's polarization (page 31), and this carrier matching is difficult to achieve using traditional semiconductors, as the relatively low density of states of conventional semiconductors prevents them from accommodating a large amount of free charge to balance polarization charge (page 28). To address these issues, Shoron teaches as a channel material lanthanum doped barium stannate (BaSnO3, pages 6 and 72). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the device of Yin by replacing the material composition of the fins according to the teachings of Cheng, such that the plurality of fins is made of doped barium stannate comprising lanthanum, barium, tin, and oxygen for proper integration of the ferroelectric layer with the semiconductor channel (see above).
Regarding claim 3, while Yin in view of Cheng teaches the device of claim 2,
Yin does not teach that the plurality of spacers comprise barium, tin, and oxygen.
Cheng, on the other hand, discloses that while BSO (BaSnO3) is a promising candidate as a semiconducting channel material for high performance field effect transistors (page 1, col. 1, para. 1) common perovskite oxide substrates have a large lattice mismatch with BSO, resulting in a high threading dislocation density (page 1, col. 1, para. 1). Accordingly, Cheng teaches a method of growing of functional epitaxial layers of La doped BaSnO3 as channel layers (Fig. 2; page 5, col. 1, para. 2a) for ferroelectric field effect transistors, wherein the method comprises growing an unintentionally doped BSO (BaSnO3) buffer layer between the substrate and the La-doped BaSnO3 channel layer (Fig. 2a, page 3, col. 1, para. 3), which comprises barium, tin, and oxygen.
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the undoped BaSnO3 is an insulator and would be motivated to modify the device of Yin in view of Cheng to form the spacers between the BaSnO3 fins (modified to be BaSnO3 in Yin in view of Cheng, see claim 2) so that the lattice mismatch between the fins and spacers are minimized. Thus, the combination of Yin and Cheng further teaches that the plurality of spacers comprise barium, tin, and oxygen.
Regarding claim 4, Yin in view of Cheng teaches the device of claim 3, wherein
the combination of Yin and Cheng further teaches that a density of lanthanum in the plurality of spacers (undoped, see claim 3 rejection above) is less than 10% of a density of lanthanum in the plurality of fins (doped with lanthanum, see claims 2-3 rejections above).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yin (CN 113178491 A) as applied to claims 1 and 6 above, and further in view of Chen (US 2020/0328287 A1).
Regarding claim 5, Yin teaches the device of claim 1, wherein the plurality of spacers are an undoped semiconductor (support structures 201, [0038]: Si for P-type NC-FET or SiGe for N-type NC-FET).
Yin, however, does not teach that the plurality of fins are a doped semiconductor.
Chen, on the other hand, teaches a device (semiconductor device, Fig. 15A-C, [0076]; the semiconductor device is a negative capacitance FET [0046]), wherein the channel region (channel 214, corresponding to fins under the gate in Yin, Fig. 15C, [0071]) is a doped semiconductor ([0052]: N-type silicon ([0038]) in N-type NCFET).
Therefore, negative capacitance FETs with doped semiconductor (silicon as the bulk material in the case of Yin and Chen) is known in the field, and the negative capacitance FET of Yin can also be formed by doped silicon (semiconductor) fins. Therefore, it would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the techniques to improve the negative capacitance FETs of Yin (by forming the device in a fishbone design structure) can also be applied to negative capacitance FETs with doped fins, and accordingly a person of ordinary skill in the art before the effective filing date of the claimed invention could have substituted the undoped fins of Yin with doped fins as disclosed by Chen (see MPEP 2143(I)(C) and MPEP 2143(I)(D)).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yin (CN 113178491 A) as applied to claims 1 and 6 above.
Regarding claim 7, Yin teaches the device of claim 6, wherein the dielectric layer (high interface oxide layer 104 and ferroelectric layer 110, Fig. 12, [0063]) comprises an interlayer (high interface oxide layer 104, Fig. 12), wherein the interlayer (high interface oxide layer 104, Fig. 12) is a linear dielectric ([0063]: SiO2 which is a linear dielectric),
wherein the interlayer (high interface oxide layer 104, Fig. 12) is adjacent the plurality of fins (nanosheets 202, Figs. 12),
wherein the ferroelectric layer (ferroelectric layer 110, Fig. 12) is adjacent the interlayer (high interface oxide layer 104, Fig. 12),
wherein the gate (metal gate 105, Fig. 12) is adjacent the ferroelectric layer (ferroelectric layer 110, Fig. 12).
Yin, on the other hand, is silent on that
the interlayer bridges a lattice mismatch between the plurality of fins and the ferroelectric layer.
However, Zhou (CN 105826175 A) teaches a transistor comprising a silicon layer (fin 101, Fig. 7, [0066]-[0067]; the material of fins in Yin) and a hafnium oxide layer (hafnium oxide layer 107 as gate dielectric, Fig. 7, [0076; ]; the material of ferroelectric layer in Yin). Zhou further discloses that “if the hafnium oxide layer 107 is in direct contact with the silicon substrate 100, lattice mismatch is likely
to occur between hafnium atoms and silicon atoms, and interface state defects are more likely to occur.
Therefore, …. , a silicon oxide layer 106 is formed between the hafnium oxide layer 107 and the silicon substrate 100, and there are fewer interface state defects between the silicon oxide layer
106 and the silicon substrate 100.” Thus, the silicon dioxide interlayer in Yin bridges the lattice mismatch between the silicon fins and hafnium oxide ferroelectric layer, and the organization of layers in Yin meets all the limitations of claim 7.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yin (CN 113178491 A) as applied to claims 1 and 6 above, and further in view of Amrouch (Amrouch et al., Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance, in IEEE Access, vol. 6, pp. 52754-52765, 2018, doi: 10.1109/ACCESS.2018.2870916).
Regarding claim 8, while Yin teaches the device of claim 1,
Yin does not teach a processor comprising the device of claim 1.
Amrouch, on the other hand, teaches how far NCFET technology will enable processors (1) to operate at higher frequencies without increasing voltage; (2) to operate at higher frequencies without increasing power density; and (3) to operate at lower voltages, while still fulfilling performance requirements (Abstact). Amrouch discloses that negative capacitance field-effect transistor (NCFET) can provide a quantum leap in computing efficiency, because it enables processors to operate at higher frequencies, without increasing the operating voltage (page 10, Conclusion).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the device of claim 1 is an NCFET which can be used in a processor to improve performance of the processor, as taught by Amrouch, and therefore a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to employ the NCFET device of Yin in a processor. Thus, the combination of Yin and Amrouch meets the limitations of claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cao (CN 113178490 A) teaches a ferroelectric tunneling field effect transistor with a fishbone structure, which is relevant to all claims.
Cheng (Cheng et al., Nanoscale etching of perovskite oxides for field effect transistor applications. J. Vac. Sci. Technol. B 1 January 2020; 38 (1): 012201. https://doi.org/10.1116/1.5122667) teaches perovskite oxides for field effect transistors, which is relevant to claims 2-5.
Cheng (Cheng et al., High-Current Perovskite Oxide BaTiO3/BaSnO3 Heterostructure Field Effect Transistors, in IEEE Electron Device Letters, vol. 41, no. 4, pp. 621-624, April 2020, doi: 10.1109/LED.2020.2976456) teaches BaTiO3/BaSnO3 heterostructure field effect transistors, which is relevant to claims 2-5.
Yue (Yue et al., Depletion Mode MOSFET Using La-Doped BaSnO3 as a Channel Material, ACS Applied Materials & Interfaces 2018 10 (25), 21061-21065 DOI: 10.1021/acsami.8b05229) teaches lanthanum doped barium stannate as a channel material, which is relevant to claims 2-5.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812