DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group[ I and Species B in the reply filed on 12/15/2025 is acknowledged.
Claims 7-8 and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/15/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s)1-6 and 9-14 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 9, the limitation “a source region and a drain region positioned on opposing sides of a channel region in the stack of sheet semiconductor layers,” is unclear as to what element(s) are “in the stack of sheet semiconductor layers,” i.e. the source/drain regions, the channel region, or the source/drain regions and the channel region.
Regarding claims 1 and 9, the limitation “a first contact to an upper sheet portion of the source and drain regions for the stack of sheet semiconductor layers” is unclear as to what is required by “an upper sheet portion,” and “for the stack of sheet semiconductor layers.” Specifically, it is noted that the first contact is understood to contact the source/drain epitaxy region and not the upper sheet(s). It is therefore unclear as to what is required by “to.” Additionally, it is unclear if “for the stack of sheet semiconductor layers” is intended to require the contact is for the source/drain regions which include the stack of sheet semiconductor layers, or if the claim is intended to require that the contact is to the source/drain region but for the channel region of the sheet semiconductor layers. Lastly, it is unclear as to how a first contact (single) is “to source and drain regions” (plural).
Regarding claims 1 and 9, the limitation “an upper sheet portion of the source and drain regions… a lower sheet portion of a source/drain region” is unclear as to what is required by the claim. Specifically, it is noted that the source/drain regions are understood from the specification to be epitaxy regions, so it is unclear what is required by the limitation to the “upper sheet portion” and “lower sheet portion” of the source/drain regions. It is additionally unclear as to if it requires an upper (lower) portion for each of the source and drain regions, or a single sheet portion in one of the source or drain region.
Regarding claims 1 and 9, the limitation “an extended epitaxial semiconductor region in contact with a lower sheet portion of a source/drain region portion for the stack of sheet semiconductor layers” is unclear as to what is required by “for the stack of sheet semiconductor layers.” Specifically, it is noted that the source/drain regions are understood from the specification to be epitaxy regions and the extended epitaxial region is understood to contact the source/drain epitaxial region. It is therefore unclear as to what is required by “to.” Additionally, it is unclear if “for the stack of sheet semiconductor layers” is intended to require the extended epitaxial semiconductor region is for the source/drain regions which include the stack of sheet semiconductor layers, or if the claim is intended to require that the extended epitaxial semiconductor region is in contact with the source/drain region but for the channel region of the sheet semiconductor layers.
Regarding claims 1 and 9, the limitation “a source/drain region portion,” is unclear as to how it is related to the “a source region and a drain region,” previously recited.
Regarding claims 3 and 11, the limitation “the upper sheet portion that the first contact is in contact with is in the first region,” is unclear because the first contact has not previously been claimed as being in contact with the upper sheet portion. Rather, claim recites the first contact is “to” the upper sheet portion. It is therefore unclear as to if the recitation of the instant claim carries additional weight, and as to the proper interpretation of “to” and “in contact with.”
Regarding claims 3 and 11, the limitation “the sheet semiconductor layers a first region…” appears to contain a typographical error which renders the meaning of the limitation indefinite.
Regarding claims 3 and 11, the limitation “the lower sheet portion that the second contact is in contact with is in the second region,” is unclear because the second contact has not been previously claimed as being in contact with the lower sheet portion. Rather, the second contact is claimed as being “in direct contact with an upper surface of the extended epitaxial semiconductor region.”
Regarding claims 4 and 12, the limitation “the lower sheet portion is a bottom sheet source/drain epitaxy material,” is unclear as to what is required. Specifically, the source/drain regions are understood as epitaxial material encompassing the sheets (see, e.g. [0027] of applicant’s specification). It is therefore unclear as to how the “sheet portion,” which would seem to imply it is sheets semiconductor layers,” are being claimed as the same thing as the “epitaxial material.”
Regarding claims 6 and 14, the limitation “the upper sheet portion of the source and drain regions is an upper sheet epitaxy semiconductor material,” is unclear as to what is required. Specifically, the source/drain regions are understood as epitaxial material encompassing the sheets (see, e.g. [0027] of applicant’s specification). It is therefore unclear as to how the “sheet portion,” which would seem to imply it is sheets semiconductor layers,” are being claimed as the same thing as the “epitaxial material.”
Regarding claim 9, the limitation “a second contact in direct contact with an upper surface of the extended epitaxial semiconductor region,” is unclear as to how it is related to the previously recited “upper surface” of the extended epitaxial semiconductor region.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 11069684; herein “Xie”).
Regarding claim 1, Xie teaches in Fig. 14 and related text a semiconductor device comprising:
a stack of sheet semiconductor layers (106a/b, see col. 4 line 60);
a source region and a drain region (126/130, see col. 7 line 52 and col. 8 line 50) positioned on opposing sides (see Fig. 1 and related text) of a channel region in the stack of sheet semiconductor layers,
a first contact (138, see col. 9 line 42-43) to an upper sheet portion of the source and drain regions (130) for the stack of sheet semiconductor layers;
an extended epitaxial semiconductor region (region of 126 which extends to 140) in contact with a lower sheet portion of a source/drain region portion (126) for the stack of sheet semiconductor layers: and
a second contact (140, see col. 9 line 43) in direct contact with an upper surface of the extended epitaxial semiconductor region.
Regarding claim 2, Xie further discloses wherein the sheet semiconductor layers (106a/b) are nanosheets (col. 4 line 60).
Regarding claim 3, Xie further disclose wherein the sheet semiconductor layers a first region of nanosheets (106b) at a first height and a second region of nanosheets (106a) at a second height, wherein the second height is less than the first height, the upper sheet portion that the first contact (138) is in contact with is in the first region (130), and the lower sheet portion that the second contact (140) is in contact with is in the second region (126).
Regarding claim 4, Xie further discloses wherein the lower sheet portion (126) is a bottom sheet source/drain epitaxy material (see col. 7 lines 51-55).
Regarding claim 6, Xie further discloses wherein the upper sheet portion of the source and drain regions (130) is an upper sheet epitaxy semiconductor material that is doped to an n- type or p-type conductivity (see col. 7 lines 51-55 and col. 8 lines 54-56).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 and 9-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Lee et al. (US 20220359682; herein “Lee”).
Regarding claim 5, Xie substantially discloses the invention as applied to claim 1, but does not disclose wherein the extended epitaxial semiconductor region has a higher dopant concentration for n-type or p-type dopant than the bottom sheet source/drain epitaxy material.
In the same field of endeavor, Lee teaches in Fig. 11A and related text a semiconductor device comprising
an epitaxial semiconductor region in contact with a source/drain region portion (146, see [0028]) for the stack of sheet semiconductor layers (see [0011]),
a second contact (176/178, see [0055]-[0056]) in direct contact with an upper surface of the epitaxial semiconductor region;
the epitaxial semiconductor region has a higher dopant concentration for n-type or p-type dopant than the bottom source/drain epitaxy material (e.g. the top region 146 in direct contact with the second contact has a higher dopant concentration than the lower portion of the source/drain epitaxy, see [0029]-[0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie by having the epitaxial semiconductor region has a higher dopant concentration for n-type or p-type dopant than the bottom source/drain epitaxy material, as shown by Lee, in order to provide an improved contact structure with improved device performance (see Lee [0010] at least). The limitation “the epitaxial semiconductor region has a higher dopant concentration for n-type or p-type dopant than the bottom sheet source/drain epitaxy material,” is therefore taught by the combination of the upper and lower portions of the source/drain epitaxial region having the respective concentrations surrounding the second contact, as shown by Lee, and the second contact being in contact with the extended epitaxial region, as shown by Xie.
Regarding claim 9, Xie teaches in Fig. 14 and related text a semiconductor device comprising:
a stack of sheet semiconductor layers (106a/b, see col. 4 line 60);
a source region and a drain region (126/130, see col. 7 line 52 and col. 8 line 50) positioned on opposing sides (see Fig. 1 and related text) of a channel region in the stack of sheet semiconductor layers,
a first contact (138, see col. 9 line 42-43) to an upper sheet portion of the source and drain regions (130) for the stack of sheet semiconductor layers;
an extended epitaxial semiconductor region (region of 126 which extends to 140) in contact with a lower sheet portion of a source/drain region portion (126) for the stack of sheet semiconductor layers, the extended epitaxial semiconductor region includes an upper surface; and
a second contact (140, see col. 9 line 43) in direct contact with an upper surface of the extended epitaxial semiconductor region.
Xie does not disclose
the extended epitaxial semiconductor region includes the upper surface with a notch; and
wherein the second contact is in direct contact with both a sidewall surface and a base surface of the notch.
In the same field of endeavor, Lee teaches in Fig. 11A and related text a semiconductor device comprising
an epitaxial semiconductor region in contact with a source/drain region portion (146, see [0028]) for the stack of sheet semiconductor layers (see [0011]), the epitaxial semiconductor region includes an upper surface upper surface with a notch (see Fig. 11A); and
a second contact (176/178, see [0055]-[0056]) in direct contact with an upper surface of the epitaxial semiconductor region, wherein the second contact is in direct contact with both a sidewall surface and a base surface of the notch (see Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie by having the epitaxial semiconductor region includes the upper surface with a notch and the second contact in direct contact with both a sidewall surface and a base surface of the notch, as shown by Lee, in order to provide an improved contact structure with improved device performance (see Lee [0010] at least). The limitations “the extended epitaxial semiconductor region includes the upper surface with a notch,” and “the second contact is in direct contact with both a sidewall surface and a base surface of the notch,” are therefore taught by the combination of the notch of the epitaxial region and the second contact in contact with the notch, as shown by Lee, and the second contact being in contact with the extended epitaxial region, as shown by Xie.
Regarding claims 10-14, Xie further discloses the claimed limitation in the same manner as applied to claims 2-6 above, respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 1/16/2026