Prosecution Insights
Last updated: July 17, 2026
Application No. 17/956,486

LOW-COST SURFACE MOUNT EMI GASKETS

Final Rejection §103
Filed
Sep 29, 2022
Examiner
PALANISWAMY, KRISHNA JAYANTHI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
14 granted / 19 resolved
+5.7% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
20 currently pending
Career history
47
Total Applications
across all art units

Statute-Specific Performance

§103
90.9%
+50.9% vs TC avg
§102
3.0%
-37.0% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 19 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s amendments to claims 1, 9, and 16 have been fully considered. Based on the cited prior arts Han, Lin, Phillips, Arnold, and new grounds of rejection from Lee (KR20110081363A) the claims 1-5, 8-16, 19-21 are rejected. Response to Amendments Applicant’s amendments to the claims 16 and 21 have been fully considered and resolve the claim objections. The claim objections have been withdrawn. Applicant’s amendments to the specification has been fully considered and resolve the specification objection. The specification objection has been withdrawn. Applicant’s cancellation of claims 6, 7, 17, and 18 has been acknowledged. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3 - 5, 8 – 10, and 13 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US20200027844A1; hereinafter Han). in view of Lee et al. (KR20110081363A; hereinafter Lee). Regarding Claim 1, Han discloses an integrated circuit package (integrated circuit package [0001]), comprising: a substrate (substrate 106p) comprised of a metallic ground layer (ground 126b), FIG. 13C reproduced below, [0093]; one or more dies disposed on the substrate (the component on the substrate can be a radiation source and/or radiation sensitive device, radiation source 110 on substrate 106p), FIG. 13C, [0093]; and a plurality of electrically conductive compressible gaskets. Han [0057] discloses the package can have one or more ground coupling mechanisms between the ground on the substrate and the heat spreader; and [0091] discloses the ground coupling mechanism 124e may be a conductive gasket, FIG. 13C, indicating the package comprises a plurality of electrically conductive compressible gaskets. wherein the electrically conductive compressible gaskets (124e) are positioned to contact a plate (heat spreader 122e, [0048]) and electrically ground the plate when the plate is secured to the package (System on chip (SoC) package), FIG. 13C, [0093]. PNG media_image1.png 335 768 media_image1.png Greyscale Han: FIG. 13C Han does not disclose “individuals of which comprise a copper foil on a surface that contacts the metallic ground layer and are soldered thereto.” In the same field of endeavor, Lee discloses an electrically conductive connector composed of an elastic body and metal foil, possessing electrical conductivity and elastic force for electromagnetic wave shielding and grounding [0014]. Lee [0014] discloses an electrically conductive connector 50 that is solderable and composed of an elastic body and metal foil, possessing electrical conductivity and elastic force for electromagnetic wave shielding and grounding. Lee discloses the connector 50 comprises a conductive elastomer 30 forming an internal cushioning material, an electrically conductive fiber or metal foil 40 attached to the upper surface of the elastic body 30, and a metal foil 20 on the lower surface. The elastomer 30 provides cushioning force and elasticity while maintaining electrical conductivity. Thus, the connector 50 functions as an electrically conductive compressible gasket, FIG.1 reproduced below, [0046], [0047]. Lee discloses the lower surface of connector 50 is soldered to the soldering pad 500 of the PCB 400 through solder 600 and the upper surface is connected to a metal case 800, FIG. 3 reproduced below, [0062]. Han discloses the electrically conductive gaskets 124e is coupled with ground 126b on substrate 106p, FIG. 13C, [0093]. The combination of Han and Lee discloses: individuals of which comprise a copper foil (Lee: connector 50 with metal foil 20 made of copper [0040]) on a surface that contacts the metallic ground layer (Han: 126b, FIG. 13C, [0093]) and are soldered thereto (Lee: soldering 600, FIG. 3, [0062]). PNG media_image2.png 474 486 media_image2.png Greyscale Lee: FIG. 1 PNG media_image3.png 374 760 media_image3.png Greyscale Lee: FIG. 3 Lee discloses that the electrically conductive compressible connector as taught improves solderability, electrical conductivity, EMI shielding and reduces manufacturing cost [0001], [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s package to improve solderability, electrical conductivity, EMI shielding and reduce manufacturing cost as disclosed by Lee [0001], [0014]. Regarding Claim 3, The combination of Han and Lee discloses the package of claim 1. Han discloses: further comprising a stiffener (ground 126 can be a stiffener, [0070]) disposed around a perimeter of the integrated circuit package and defining an interior space (ground 126 can extend around one or more of radiation sources 110a and 110b and one or more radiation sensitive devices 112a and 112b, [0079], FIG. 8A), wherein the plurality of electrically conductive compressible gaskets are located within the interior space (the ground can include a protruded stiffener to contain and make contact with a conductive gasket, [0059], FIG. 8B). Regarding Claim 4, The combination of Han and Lee discloses the package of claim 3. Han discloses: wherein at least one of the plurality of electrically conductive compressible gaskets (124e) is in contact with the stiffener (126b), (the ground can include a protruded stiffener to contain and make contact with a conductive gasket, [0059]), FIG. 13C. Regarding Claim 5, The combination of Han and Lee discloses the package of claim 1. Han discloses: wherein individuals of the electrically conductive compressible gaskets (124e, FIG. 13C) have dimensions of 1mm width by 0.5mm length by 0.4-0.5mm height [0057]. Han [0057] discloses the force generated by the mechanically compliant electrically conductive gasket between a ground on the substrate and a heat spreader can be controllable by virtue of the geometry of the gaskets (e.g., width, length, incident angle, material, etc.). It would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to include electrically conductive compressible gaskets which have dimensions of 1mm width by 0.5mm length by 0.4-0.5mm height for routine optimization to meet packaging requirements. Regarding Claim 8, The combination of Han and Lee discloses the package of claim 1. Han discloses: wherein the plurality of electrically conductive compressible gaskets (124e) comprises from four to six gaskets. Han [0057] discloses the package can have one or more ground coupling mechanisms between the ground on the substrate and the heat spreader. Han [0091] discloses the ground coupling mechanism 124e may be a conductive gasket (FIG. 13C), indicating the plurality of electrically compressible gaskets can comprise from four to six gaskets. Regarding Claim 9, Han discloses a system for EMI shielding of an integrated circuit package (this structure creates a package-level Faraday shielding cage that blocks die and package radiation and is able to offer shielding solutions for SoCs and disaggregated SoCs/package, [0049]), comprising: an integrated circuit package (SoC package, [0049]); and a plurality of electrically conductive compressible gaskets (124e, [0057], [0091]) sized to contact a cold plate (heat spreader 122e can be a cold plate, [0048]) when the cold plate is disposed upon the integrated circuit package FIG. 13C, [0093]. Han [0057] discloses the package can have one or more ground coupling mechanisms between the ground on the substrate and the heat spreader; and [0091] discloses the ground coupling mechanism 124e may be a conductive gasket, indicating the package comprises a plurality of electrically conductive compressible gaskets. Han [0060] discloses the conductive gasket may be applied to the heat spreader and/or the grounded package stiffener; and [0048] discloses the stiffener is electrically grounded to the package ground plan (Vss), indicating the conductive compressible gaskets are electrically bonded to a ground plane of the integrated circuit package. wherein the cold plate (122e) is electrically connected to the ground plane (Vss) when in contact with the plurality of electrically conductive compressible gaskets (124e), FIG. 13C, [0060], [0048]. Han does not disclose “individuals of which comprise a copper foil on a surface that contacts a ground plane of the integrated circuit package and are soldered thereto.” In the same field of endeavor, Lee discloses an electrically conductive connector composed of an elastic body and metal foil, possessing electrical conductivity and elastic force for electromagnetic wave shielding and grounding [0014]. Lee [0014] discloses an electrically conductive connector 50 that is solderable and composed of an elastic body and metal foil, possessing electrical conductivity and elastic force for electromagnetic wave shielding and grounding. Lee discloses the connector 50 comprises a conductive elastomer 30 forming an internal cushioning material, an electrically conductive fiber or metal foil 40 attached to the upper surface of the elastic body 30, and a metal foil 20 on the lower surface. The elastomer 30 provides cushioning force and elasticity while maintaining electrical conductivity. Thus, the connector 50 functions as an electrically conductive compressible gasket, FIG.1, [0046], [0047]. Lee discloses the lower surface of connector 50 is soldered to the soldering pad 500 of the PCB 400 through solder 600 and the upper surface is connected to a metal case 800, FIG. 3, [0062]. The combination of Han and Lee discloses: individuals of which comprise a copper foil (Lee: connector 50 with metal foil 20 made of copper [0040]) on a surface that contacts a ground plane of the integrated circuit package (Han: ground plane VSS of the SoC package, [0048], [0060]) and are soldered thereto (Lee: soldering 600, FIG. 3, [0062]). Lee discloses that the electrically conductive compressible connector as taught improves solderability, electrical conductivity, EMI shielding and reduces manufacturing cost [0001], [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s package to improve solderability, electrical conductivity, EMI shielding and reduce manufacturing cost as disclosed by Lee [0001], [0014]. Regarding Claim 10, The combination of Han and Lee discloses the system of claim 9. Han discloses: further comprising the cold plate (122e) disposed upon the integrated circuit package (SoC package) that compresses the plurality of electrically conductive compressible gaskets (124e), FIG. 13C, [0093]. Regarding Claim 13, The combination of Han and Lee discloses the system of claim 10. Han discloses: wherein the cold plate (122e) has a plurality of recessed pockets corresponding to the plurality of electrically conductive compressible gaskets (124e), [0060]. Han [0060] discloses the cold plate (122e) may have grooves or altered surface for containing the conductive gasket. Han (FIG. 15A, [0097]) also discloses the gaskets 124g can be a recessed slit or a groove formed into heat spreader 122g. Regarding Claim 14, The combination of Han and Lee discloses the system of claim 10. Han discloses: wherein the system further comprises a laptop computer [0064]. Regarding Claim 15, The combination of Han and Lee discloses the system of claim 9. Han discloses: further comprising a stiffener disposed upon the integrated circuit package (ground 126 can be stiffener on substrate 106e of the SoC package, FIG. 2C, [0070]) that surrounds the plurality of electrically conductive compressible gaskets (ground 126 can extend around one or more of radiation sources 110a and 110b and one or more radiation sensitive devices 112a and 112b, FIG. 8A, [0079]). Regarding Claim 16, Han discloses a method [0039], comprising: disposing a plurality of electrically conductive compressible gaskets (124e, [0057], [0091]) upon a conductive ground layer (126b) of an integrated circuit package (SoC package); disposing a cold plate (heat spreader 122e can be a cold plate, [0048]) upon a die of the integrated circuit (110 on SoC package) such that the cold plate (122e) contacts the plurality of electrically conductive compressible gaskets (124e) and creates an electrically conductive path from the cold plate (122e) to the ground layer (126b), FIG. 13C, [0093]; and compressing, with the cold plate (122e), the plurality of electrically conductive compressible gaskets (124e), FIG. 13C, [0093]. Han does not disclose “individuals of which comprise a copper foil on a surface that contacts the conductive ground layer; soldering the individuals to the conductive ground layer.” In the same field of endeavor, Lee discloses an electrically conductive connector composed of an elastic body and metal foil, possessing electrical conductivity and elastic force for electromagnetic wave shielding and grounding [0014]. Lee [0014] discloses an electrically conductive connector 50 that is solderable and composed of an elastic body and metal foil, possessing electrical conductivity and elastic force for electromagnetic wave shielding and grounding. Lee discloses the connector 50 comprises a conductive elastomer 30 forming an internal cushioning material, an electrically conductive fiber or metal foil 40 attached to the upper surface of the elastic body 30, and a metal foil 20 on the lower surface. The elastomer 30 provides cushioning force and elasticity while maintaining electrical conductivity. Thus, the connector 50 functions as an electrically conductive compressible gasket, FIG.1, [0046], [0047]. Lee discloses the lower surface of connector 50 is soldered to the soldering pad 500 of the PCB 400 through solder 600 and the upper surface is connected to a metal case 800, FIG. 3, [0062]. Han [0060] discloses the conductive gasket may be applied to the heat spreader and/or the grounded package stiffener; and [0048] discloses the stiffener is electrically grounded to the package ground plan (Vss), indicating the conductive compressible gaskets are electrically bonded to a ground plane of the integrated circuit package. The combination of Han and Lee discloses: individuals of which comprise a copper foil on a surface (Lee: connector 50 with metal foil 20 made of copper [0040]) that contacts the conductive ground layer (Han: ground plane VSS of the SoC package, [0048], [0060]); soldering the individuals (Lee: soldering 600, FIG. 3, [0062]), to the conductive layer (Han: VSS). Lee discloses that the electrically conductive compressible connector as taught improves solderability, electrical conductivity, EMI shielding and reduces manufacturing cost [0001], [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han’s package to improve solderability, electrical conductivity, EMI shielding and reduce manufacturing cost as disclosed by Lee [0001], [0014]. Claims 11, 12, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Han in view Lee, further in view of Lin et al. (US20220186835A1; hereinafter Lin). Regarding Claim 11, The combination of Han and Lee discloses the system of claim 10. Han and Lee does not disclose “wherein individuals of the electrically conductive compressible gaskets are compressed from between 16% to 52% from their uncompressed height.” The combination of Han, Lee, and Lin discloses: wherein individuals of the electrically conductive compressible gaskets (Han:124e, FIG. 13C, [0093]) are compressed from between 16% to 52% from their uncompressed height (Lin [0034]: a gasket may be compressed to about 15%-60% of its original (uncompressed) state (e.g., height in the Z-direction)). Lin discloses that the electrically conductive compressible gasket as taught may have good compression and resiliency [0034]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han and Lee’s package to provide electrically conductive gaskets with improved compression and resiliency as disclosed by Lin [0034]. Regarding Claim 12, The combination of Han and Lee discloses the system of claim 10. Han and Lee does not disclose “wherein the cold plate is biased towards the integrated circuit package at a pressure of 10 psi.” The combination of Han, Lee, and Lin disclose: wherein the cold plate (Han: 122e, FIG. 13C, [0093]) is biased towards the integrated circuit package (Han: SoC package) at a pressure of 10 psi (Lin: FIG. 5, [0013]). Lin FIG. 5 discloses a line graph of pressure (N/cm2) versus displacement (percentage compression ratio) with pressure values in the range of approximately 5.8 psi (4N/cm2) to 101 psi (70N/cm2), indicating the cold plate (Han: 122e) may be biased towards the integrated circuit package (Han: SoC package) at a pressure of 10psi (6.9N/cm2). Lin discloses that the electrically conductive compressible gasket as taught may have good compression and resiliency [0034]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han and Lee’s package to provide electrically conductive gaskets with improved compression and resiliency as disclosed by Lin [0034]. Regarding Claim 20, The combination of Han and Lee discloses the method of claim 16. Han and Lee does not disclose “wherein compressing the plurality of electrically conductive compressible gaskets comprises compressing the plurality of electrically conductive compressible gaskets to between 16% to 52% of their uncompressed height.” The combination of Han, Lee, and Lin disclose: wherein compressing the plurality of electrically conductive compressible gaskets comprises compressing the plurality of electrically conductive compressible gaskets (Han:124e, FIG. 13C, [0093]) to between 16% to 52% of their uncompressed height (Lin [0034]: a gasket may be compressed to about 15%-60% of its original (uncompressed) state (e.g., height in the Z-direction)). Lin discloses that the electrically conductive compressible gasket as taught may have good compression and resiliency [0034]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han and Lee’s device to provide a package with improved compression and resilient gaskets as disclosed by Lin [0034]. Regarding Claim 21, The combination of Han, Lee, and Lin disclose the method of claim 20. The combination of Han and Lee does not disclose “wherein compressing the plurality of electrically conductive compressible gaskets comprises compressing the cold plate onto the die of the integrated circuit to a pressure of 10 psi.” The combination of Han, Lee, and Lin discloses: wherein compressing the plurality of electrically conductive compressible gaskets (Han: 124e) comprises compressing the cold plate (Han: 122e) onto the die of the integrated circuit package (Han: 110 on the SoC package, FIG. 13C, [0093]) to a pressure of 10 psi (Lin: FIG. 5, [0013]). Lin FIG. 5 discloses a line graph of pressure (N/cm2) versus displacement (percentage compression ratio) with pressure values in the range of approximately 5.8 psi (4N/cm2) to 101 psi (70N/cm2), indicating the cold plate (Han: 122e) may be biased towards the integrated circuit package (Han: SoC package) at a pressure of 10psi (6.9N/cm2). Lin discloses that the electrically conductive compressible gasket as taught may have good compression and resiliency [0034]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the package to provide electrically conductive gaskets with improved compression and resiliency as disclosed by Lin [0034]. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view Lee, further in view of Phillips (US20080171469A1; hereinafter Phillips). Regarding Claim 2, The combination of Han and Lee discloses the package of claim 1. The combination of Han and Lee does not disclose “wherein the substrate is overlaid with a non-conductive layer, the non-conductive layer having a plurality of apertures, individuals of the plurality of gaskets placed in corresponding individuals of the plurality of apertures.” In a similar art, Phillips discloses electrical connector assemblies with EMI gaskets [0005]. The combination of Han, Lee, and Phillips disclose: wherein the substrate (Han:106p, FIG. 13C, [0093]) is overlaid with a non-conductive layer (Phillips: dielectric body 80, FIG. 1, [0021]), the non-conductive layer having a plurality of apertures (Phillips: plurality of slots 116, FIG. 5, [0025]), individuals of the plurality of gaskets (Phillips: EMI gasket 16 including 76 and 88, FIG. 4, [0021]) placed in corresponding individuals of the plurality of apertures (Phillips: [0025]). Phillips discloses that a structure as taught facilitates minimizing EMI emissions while maintaining structural integrity [0034]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han and Lee’s package, to minimize EMI emissions while maintaining structural integrity as disclosed by Phillips [0034]. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Lee, further in view of Arnold et al. (US20040240191A1; hereinafter Arnold). Regarding Claim 19, The combination of Han and Lee discloses the method of claim 16. The combination of Han and Lee does not disclose “wherein disposing the plurality of electrically conductive compressible gaskets upon the ground layer comprises disposing the plurality of electrically conductive compressible gaskets within a plurality of apertures in an insulating layer that expose the ground layer.” In a similar art, Arnold discloses EMI shielded electronic devices and printed circuit boards [0003]. The combination of Han, Lee, and Arnold disclose: wherein disposing the plurality of electrically conductive compressible gaskets (Han: 124e, FIG. 13C, [0093]) upon the ground layer (Han: 126b) comprises disposing the plurality of electrically conductive compressible gaskets within a plurality of apertures (Arnold: vias 54, FIG. 4, [0076]) in an insulating layer (Arnold: insulating PCB 10) that expose the ground layer (Arnold: ground plane 20). Arnold discloses that a structure as taught improves EMI shielding of electronic components on a printed circuit board [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Han and Lee’s package, to improve EMI shielding of the electronic components as disclosed by Arnold [0014]. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Krishna J Palaniswamy whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-483-7639. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent- center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Krishna J Palaniswamy/ Examiner, Art Unit 2899 /Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Sep 29, 2022
Application Filed
Apr 26, 2023
Response after Non-Final Action
Nov 12, 2025
Non-Final Rejection mailed — §103
Feb 12, 2026
Response Filed
Jun 01, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
99%
With Interview (+33.3%)
3y 1m (~0m remaining)
Median Time to Grant
Moderate
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