DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-20, in the reply filed on 12/17/25 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-9 and 11-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Monadgemi (US 2022/0208728).
Regarding claim 1, Monadgemi discloses a package comprising:
a substrate (110, fig. 1 and paragraph 0016) with a first side and a second side opposite the first side, wherein the substrate includes a redistribution layer (paragraph 0017);
a die on the first side of the substrate, wherein the die is electrically coupled with the redistribution layer (121, fig. 1 and paragraph 0017); and
a memory die on the second side of the substrate (130, fig. 1 and paragraph 0016), wherein the memory die is electrically coupled with the redistribution layer using a wire bond (132, fig. 1 and paragraph 0016), and wherein the memory die is electrically coupled with the die (paragraph 0019).
Regarding claim 2, Monadgemi further discloses a molding surrounding the
memory die, wherein the molding is physically coupled with the second side of the substrate (140, fig. 1 and paragraph 0016).
Regarding claim 3, Monadgemi further discloses an interconnect in the molding,
wherein the interconnect is electrically coupled with the redistribution layer and is electrically coupled with the die (132, fig. 1 and paragraph 0016).
Regarding claim 4, Monadgemi further discloses wherein the interconnect includes a metal via (paragraph 0019).
Regarding claim 6, Monadgemi further discloses wherein a portion of the memory die (130, fig. 1) is beneath a portion of the die (121, fig. 1) with respect to a surface of the substrate (110, fig. 1).
Regarding claim 7, Monadgemi further discloses wherein the memory die is a selected one of a dynamic random access memory die, or a static random access memory die (paragraph 0016).
Regarding claim 8, Monadgemi further discloses wherein the memory die is a first memory die (130a, fig. 1), and wherein the wire bond is a first wire bond (132, fig. 1); and further comprising a second memory die (130b, fig. 1) on the second side of the substrate, wherein the second memory die is electrically coupled with the redistribution layer using a second wire bond (132, fig. 1), and wherein the second memory die is electrically coupled with the die (paragraph 0019).
Regarding claim 9, Monadgemi further discloses a molding surrounding the first
memory die and the second memory die, wherein the molding is physically coupled with the second side of the substrate (140, fig. 1 and paragraph 0016).
Regarding claim 11, Monadgemi further discloses wherein the die includes a plurality of dies (paragraph 0040).
Regarding claim 12, Monadgemi discloses a package comprising:
a substrate (110, fig. 1 and paragraph 0016) having a first side and a second side opposite the first side, wherein the substrate includes a plurality of layers, wherein at least some of the plurality of layers include an electrical routing (paragraph 0019);
a top die physically and electrically coupled with the first side of the substrate (121, fig. 1 and paragraph 0017);
a plurality of memory dies physically and electrically coupled with the second
side of the substrate (130a-d, fig. 1 and paragraph 0016), wherein the plurality of memory dies are electrically coupled with the top die through the substrate (paragraph 0019); and wherein the plurality of memory dies are at least partially surrounded by a
molding (140, fig. 1 and paragraph 0016).
Regarding claim 13, Monadgemi further discloses wherein the top die includes a selected one or more of: a system on chip, a graphics processor unit or a central processing unit (paragraph 0017).
Regarding claim 14, Monadgemi further discloses wherein at least a portion of at least one of the plurality of memory dies is underneath the top die with respect to the first side of the substrate (fig. 1).
Regarding claim 15, Monadgemi further discloses wherein the plurality of memory dies have a first side and a second side opposite the first side, wherein the first side of the memory dies are coupled with the second side of the substrate (fig. 1).
Regarding claim 16, Monadgemi further discloses wherein the second side of one of the memory dies is thermally coupled with a thermally conductive material, wherein the thermally conductive material includes a selected one or more of: solder balls or a metal plate that includes copper (paragraph 0024).
Regarding claim 17, Monadgemi further discloses wherein at least some of the plurality of memory dies are electrically coupled with the electrical routing of the at least some of the plurality of layers of the substrate (paragraph 0019).
Regarding claim 18, Monadgemi further discloses wherein at least some of the plurality of memory dies are electrically coupled with the electrical routing using a wire bond (132, fig. 1 and paragraphs 0016-0019).
Regarding claim 19, Monadgemi further discloses a printed circuit board (PCB); and wherein the package is physically and electrically coupled with the PCB (paragraph 0017).
Regarding claim 20, Monadgemi further discloses a heat spreader on top of the top die, wherein the heat spreader has a first side and a second side opposite the first side, wherein the first side and the second side are substantially planar, and wherein the first side and the second side are substantially parallel (227, fig. 2 and paragraph 0026); and wherein the heat spreader is above at least a portion of the at least one of the plurality of memory dies with respect to the first side of the substrate (fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Monadgemi (US 2022/0208728).
Regarding claim 5, Monadgemi discloses the package of claim 3 as mentioned above. Monadgemi does no explicitly disclose wherein the interconnect is coupled with a capacitor. However, the use of capacitors in semiconductor packages was ubiquitous at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Regarding claim 10, Monadgemi discloses the package of claim 9, as mentioned above. Monadgemi does not explicitly disclose wherein the molding includes an epoxy resin. However, the Examiner takes official notice that epoxy resin was widely used for semiconductor molding applications and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 11088114 discloses another example of a semiconductor package with a logic die on one side of a substrate containing redistribution wiring and memory die on the other side of the substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 2/7/26