Prosecution Insights
Last updated: October 02, 2026
Application No. 17/956,760

SIDE OF A DIE THAT IS COPLANAR WITH A SIDE OF A MOLDING

Non-Final OA §102
Filed
Sep 29, 2022
Examiner
VU, VU A
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
3 (Non-Final)
92%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1258 granted / 1362 resolved
+24.4% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
45 currently pending
Career history
1381
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
46.5%
+6.5% vs TC avg
§102
31.3%
-8.7% vs TC avg
§112
15.0%
-25.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1362 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 12th, 2026 has been entered. Response to Amendment Acknowledgment is made that applicant's Amendment, filed on May 17th, 2026, has been entered. Upon entrance of the Amendment, claims 1, 12, and 17 were amended. Claims 1-10, 12-13, 15-17, and 19 are currently pending. Response to Arguments Applicant’s arguments with respect to amended features of independent claims have been considered. The new ground of rejection cites other elements in reference to meet the requirements of the claims. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 5-10, 12-13, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (U.S. Patent No. 11,916,025). Regarding to claim 1, Chen teaches a package comprising: a layer of molding (Fig. 13I, element 22); a first die in the layer of molding (Fig. 13I, element 20); a through silicon via (TSV) within the first die, wherein an end of the TSV is at a side of the first die (Fig. 13I, elements 14, please also see Fig.1D for annotations); wherein a surface of the side of the first die is in a same plane as a surface of a side of the layer of molding (Fig. 13I, top surface of the side of the first die 12 is in a same plane as a surface of a side of the layer of molding 22); and a second die coupled to the surface of the side of the first die, the second die having a lateral width greater than a lateral width of the first die (Fig. 13I, element P2, please note that the recitation “coupled” is given a broadest reasonable interpretation. It is not interpreted as a direct contact or electrical contact). Regarding to claim 2, Chen teaches the layer of molding is not in direct physical contact with the end of the TSV (Fig. 13I). Regarding to claim 3, Chen teaches the TSV is a plurality of TSV (Fig. 13I). Regarding to claim 5, Chen teaches a redistribution layer on the side of the first die and on the side of the layer of molding, wherein the redistribution layer is directly electrically coupled with the end of the TSV (Fig. 13I, element 34). Regarding to claim 6, Chen teaches the first die includes a front side routing layer, and wherein the front side routing layer in the first die is electrically coupled with the TSV (Fig. 13I, element 16). Regarding to claim 7, Chen teaches the side of the first die is a first side; and further comprising a second side of the die opposite the first side (Fig. 13I, the bottom side of the die), wherein the second side of the die includes one or more electrically conductive features (Fig. 13I, the pads on bottom side of layer 16), and wherein the one or more electrically conductive features are electrically coupled with the front side routing layer of the first die (Fig. 13I). Regarding to claim 8, Chen teaches the redistribution layer is a first redistribution layer; and further comprising a second redistribution layer electrically coupled with the one or more electrically conductive features on the second side of the first die (Fig. 13I, element 77). Regarding to claim 9, Chen teaches the layer of molding extends from the first redistribution layer to the second redistribution layer (Fig. 13I). Regarding to claim 10, Chen teaches one or more copper pillars that electrically couple the first redistribution layer and the second redistribution layer, wherein the one or more copper pillars are within the layer of molding (Fig. 13I, element 72, column 11, line 14). Regarding to claim 12, Chen teaches a package comprising: a redistribution layer (Fig. 13I, element 34); a first die on the redistribution layer (Fig. 13I, element 20), wherein the first die includes one or more TSV, wherein each end of the one or more TSV is at a side of the first die next to the redistribution layer, and wherein each end of the one or more TSV directly electrically couple with a side of the redistribution layer (Fig. 13I); and a layer of molding on the side of the redistribution layer and at least partially surrounding the first die, wherein a surface of the layer of molding at the side of the redistribution layer is in a same plane as a surface of the side of the first die (Fig. 13I, top surface of the side of the first die 12 is in a same plane as a surface of a side of the layer of molding 22); and a second die coupled to the surface of the side of the first die, the second die having a lateral width greater than a lateral width of the first die (Fig. 13I, element P2, please note that the recitation “coupled” is given a broadest reasonable interpretation. It is not interpreted as a direct contact or electrical contact). Regarding to claim 13, Chen teaches the side of the first die is a first side of the die; and further comprising a second side of the first die opposite the first side of the first die, wherein the layer of molding extends to the second side of the first die (FIG. 13I). Regarding to claim 16, Chen teaches the side of the redistribution layer is a first side; and further comprising: a second side of the redistribution layer opposite the first side (Fig. 13I); and a ball grid array electrically coupled with the second side of the redistribution layer (Fig. 13I). Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shen et al. (U.S. Patent No. 8,618,645). Regarding to claim 1, Shen teaches a package comprising: a layer of molding (Fig. 1I, element 140, column 5, lines 28-29); a first die in the layer of molding (Fig. 1I, element 130, column 5, lines 28-29); a through silicon via (TSV) within the first die, wherein an end of the TSV is at a side of the first die (Fig. 1I, element 138/I, column 5, lines 36-37); wherein a surface of the side of the first die is in a same plane as a surface of a side of the layer of molding (Fig. 1I); and a second die coupled to the surface of the side of the first die, the second die having a lateral width greater than a lateral width of the first die (Fig. 1I, element 160, column 6, lines 3-4). Regarding to claim 2, Shen teaches the layer of molding is not in direct physical contact with the end of the TSV (Fig. 1I). Regarding to claim 3, Shen teaches the TSV is a plurality of TSV (Fig. 1I). Claims 1-10, 12-13, and 15-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al. (U.S. Patent Application Publication No. 2021/0118759). Regarding to claim 1, Yu teaches a package comprising: a layer of molding (Fig. 16, Fig. 3, element 104; [0037], last 10 lines); a first die in the layer of molding (Fig. 16, Fig. 3, element 20; [0029], last 5 lines); a through silicon via (TSV) within the first die, wherein an end of the TSV is at a side of the first die (Fig. 16, Fig. 3, element 30; [0031], last 3 lines, a side is the bottom side of element 20 in the figure); wherein a surface of the side of the first die is in a same plane as a surface of a side of the layer of molding (Fig. 16, Fig. 3, bottom surface in the figure); and a second die coupled to the surface of the side of the first die, the second die having a lateral width greater than a lateral width of the first die (Fig. 16, Fig. 3, element 10; [0038], line 9). Regarding to claim 2, Yu teaches the layer of molding is not in direct physical contact with the end of the TSV (Fig. 3). Regarding to claim 3, Yu teaches the TSV is a plurality of TSV (Fig. 3). Regarding to claim 4, Yu teaches the TSV includes copper ([0030], line 18). Regarding to claim 5, Yu teaches a redistribution layer on the side of the first die and on the side of the layer of molding, wherein the redistribution layer is directly electrically coupled with the end of the TSV (Fig. 16, element 306). Regarding to claim 6, Yu teaches the first die includes a front side routing layer, and wherein the front side routing layer in the first die is electrically coupled with the TSV (Fig. 3, element 28). Regarding to claim 7, Yu teaches the side of the first die is a first side; and further comprising a second side of the die opposite the first side, wherein the second side of the die includes one or more electrically conductive features, and wherein the one or more electrically conductive features are electrically coupled with the front side routing layer of the first die (Fig. 16, the pads at the end of the vias). Regarding to claim 8, Yu teaches the redistribution layer is a first redistribution layer; and further comprising a second redistribution layer electrically coupled with the one or more electrically conductive features on the second side of the first die (Fig. 16, element 316). Regarding to claim 9, Yu teaches the layer of molding extends from the first redistribution layer to the second redistribution layer (Fig. 16). Regarding to claim 10, Yu teaches one or more copper pillars that electrically couple the first redistribution layer and the second redistribution layer, wherein the one or more copper pillars are within the layer of molding (Fig. 16). Regarding to claim 12, Yu teaches a package comprising: a redistribution layer (Fig. 16, element 316); a first die on the redistribution layer (Fig. 16, Fig. 3, element 20; [0029], last 5 lines); wherein the first die includes one or more TSV, wherein each end of the one or more TSV is at a side of the first die next to the redistribution layer, and wherein each end of the one or more TSV directly electrically couple with a side of the redistribution layer (Fig. 16, Fig. 3, element 30; [0031], last 3 lines); and a layer of molding on the side of the redistribution layer and at least partially surrounding the first die, wherein a surface of the layer of molding at the side of the redistribution layer is in a same plane as a surface of the side of the first die (Fig. 16, Fig. 3, element 104; [0037], last 10 lines); and a second die coupled to the surface of the side of the first die, the second die having a lateral width greater than a lateral width of the first die (Fig. 16, Fig. 3, element 10; [0038], line 9). PNG media_image1.png 682 1588 media_image1.png Greyscale Regarding to claim 13, Yu teaches the side of the first die is a first side of the die; and further comprising a second side of the first die opposite the first side of the first die, wherein the layer of molding extends to the second side of the first die (Fig. 16). Regarding to claim 15, Yu teaches the one or more TSV are filled with copper ([0030], line 18). Regarding to claim 16, Yu teaches the side of the redistribution layer is a first side; and further comprising: a second side of the redistribution layer opposite the first side; and a ball grid array electrically coupled with the second side of the redistribution layer (Fig. 16, element 306). Claims 1-4, 12-13, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (U.S. Patent No. 11,715,731). Regarding to claim 1, Lin teaches a package comprising: a layer of molding (Fig. 9, element 130); a first die in the layer of molding (Fig. 9, element 142); a through silicon via (TSV) within the first die, wherein an end of the TSV is at a side of the first die (Fig. 9, element 145); wherein a surface of the side of the first die is in a same plane as a surface of a side of the layer of molding (Fig. 9); and a second die coupled to the surface of the side of the first die, the second die having a lateral width greater than a lateral width of the first die (Fig. 9, second die including plurality of components 210 and 220). Regarding to claim 2, Lin teaches the layer of molding is not in direct physical contact with the end of the TSV (Fig. 9). Regarding to claim 3, Lin teaches the TSV is a plurality of TSV (Fig. 9). Regarding to claim 4, Lin teaches the TSV includes copper (column 5, lines 56-57). Regarding to claim 12, Lin teaches a package comprising: a redistribution layer (Fig. 9, element 144); a first die on the redistribution layer (Fig. 9, element 142), wherein the first die includes one or more TSV, wherein each end of the one or more TSV is at a side of the first die next to the redistribution layer, and wherein each end of the one or more TSV directly electrically couple with a side of the redistribution layer (Fig. 9, element 145); and a layer of molding on the side of the redistribution layer and at least partially surrounding the first die, wherein a surface of the layer of molding at the side of the redistribution layer is in a same plane as a surface of the side of the first die (Fig. 9, element 130); and a second die coupled to the surface of the side of the first die, the second die having a lateral width greater than a lateral width of the first die (Fig. 9, second die including plurality of components 210 and 220). Regarding to claim 13, Lin teaches the side of the first die is a first side of the die; and further comprising a second side of the first die opposite the first side of the first die, wherein the layer of molding extends to the second side of the first die (Fig. 9). Regarding to claim 15, Lin teaches the one or more TSV are filled with copper (column 5, lines 56-57). Regarding to claim 16, Lin teaches the side of the redistribution layer is a first side; and further comprising: a second side of the redistribution layer opposite the first side; and a ball grid array electrically coupled with the second side of the redistribution layer (Fig. 10). Regarding to claim 17, Lin teaches a method for creating a package, the method comprising: providing a redistribution layer (RDL) (Fig. 6, element 110); providing a first die having a first side and a second side opposite the first side (Fig. 6, element 142), wherein the die includes a through silicon via (TSV) with an end within a body of the first die proximate to the second side of the first die, and wherein the end of the TSV does not extend to the second side of the first die (Fig. 6, element 145); coupling the first side of the first die with the RDL (Fig. 6); placing a layer of molding on the second side of the first die and on the RDL, wherein the layer of molding covers the second side of the first die and covers at least a portion of the RDL (Fig. 6, element 130); performing a planarization of the layer of molding and of the first die, wherein the planarization includes removing a portion of the molding forming a planarized surface of the layer of molding and removing the second side of the first die forming a planarized surface of the first die that exposes the TSV at the planarized surface of the first die (Fig. 7); and coupling a second die to the planarized surface of the first die, the second die having a lateral width greater than a lateral width of the first die (Fig. 9, second die including plurality of components 210 and 220). Regarding to claim 19, Lin teaches the planarized surface of the layer of molding and the planarized surface of the die are in a same plane (Fig. 7). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VU A VU/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Show 1 earlier event
May 11, 2023
Response after Non-Final Action
Nov 20, 2025
Non-Final Rejection mailed — §102
Feb 17, 2026
Response Filed
Mar 12, 2026
Final Rejection mailed — §102
May 07, 2026
Response after Non-Final Action
Jun 12, 2026
Request for Continued Examination
Jun 17, 2026
Response after Non-Final Action
Aug 04, 2026
Non-Final Rejection mailed — §102 (current)

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Prosecution Projections

3-4
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+6.6%)
1y 10m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1362 resolved cases by this examiner. Grant probability derived from career allowance rate.

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