CTNF 17/956,775 CTNF 77500 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Arguments Applicant’s arguments with respect to claim(s) 1, 8 and 15 have been considered but are moot because the new ground of rejection below. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 3,4, 8, 10, 11 and 22 is/are rejected under 35 U.S.C. 102 a1 as being anticipated by Anderson et al. (US Patent 10,020,223) . Regarding claim 1 Anderson et al. disclose a plurality of conductive lines (12)(fig. 12) in a first inter-layer dielectric (lower portion of 36) layer (see marked up fig. 12 below), the plurality of conductive lines (12) on a same level and along a same direction (fig 1); a second ILD(upper portion of 36) (see marked up fig. 12 below)layer over the plurality of conductive lines and over the first ILD layer; a first conductive via (left via [col. 9 lines 35-55]) (see marked up fig. 12 below) in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines (12)(fig. 12), the first conductive via having a straight edge in the plan view perspective (fig. 1); and a second conductive via (right via[col. 9 lines 35-55] ) (see marked up fig. 12 below) in a second opening in the second ILD layer, the second conductive via in contact with a second (right 12) one of the plurality of conductive lines (fig. 12), the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines (left 12, right 12 in fig 12) , and the second conductive via having a straight edge in the plan view perspective (fig. 1), the straight edge of the second conductive via facing toward the straight edge of the first conductive via (fig. 12 and fig 1). PNG media_image1.png 398 646 media_image1.png Greyscale Regarding claim 3, Anderson et al. disclose a dielectric plug (upper portion of 36) (MPEP 2131 discloses “[t]he elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990)”) between and in contact with the straight edge of the first conductive via and the straight edge of the second conductive via (see marked up fig. 12 above), the dielectric plug along a direction orthogonal to the direction of the plurality of conductive lines (fig 12). Regarding claim 4, Anderson et al. disclose the dielectric plug has an uppermost surface co-planar with an uppermost surface of the second ILD layer (fig 12) [ CMP used, col. 10 lines 1-10]. Regarding claim 8, Anderson et al. disclose forming a plurality of conductive lines (12)(fig. 12) in a first inter-layer dielectric (lower portion of 36) layer (see marked up fig. 12 below), the plurality of conductive lines (12) on a same level and along a same direction (fig 1); forming a second ILD(upper portion of 36) (see marked up fig. 12 below)layer over the plurality of conductive lines and over the first ILD layer; forming a conductive structure (upper portion of layer 12, which is formed with the lines) in the second ILD layer; and cutting (etching , fig 9) the conductive structure to form a first conductive via in a first opening in the second ILD layer (36)(fig 12 , a first conductive via (left via [col. 9 lines 35-55]) (see marked up fig. 12 below) in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines (12)(fig. 12), the first conductive via having a straight edge in the plan view perspective (fig. 1); and a second conductive via (right via[col. 9 lines 35-55] ) (see marked up fig. 12 below) in a second opening in the second ILD layer, the second conductive via in contact with a second (right 12) one of the plurality of conductive lines (fig. 12), the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines (left 12, right 12 in fig 12) , and the second conductive via having a straight edge in the plan view perspective (fig. 1), the straight edge of the second conductive via facing toward the straight edge of the first conductive via (fig. 12 and fig 1). Regarding claim 10, Anderson et al. disclose a dielectric plug (upper portion of 36) (MPEP 2131 discloses “[t]he elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990)”) between and in contact with the straight edge of the first conductive via and the straight edge of the second conductive via (see marked up fig. 12 above), the dielectric plug along a direction orthogonal to the direction of the plurality of conductive lines (fig 12). Regarding claim 11, Anderson et al. disclose the dielectric plug has an uppermost surface co-planar with an uppermost surface of the second ILD layer (fig 12) [ CMP used, col. 10 lines 1-10]. Regarding claim 22 Anderson et al. disclose a plurality of conductive lines (12)(fig. 12) in a first inter-layer dielectric (lower portion of 36) layer (see marked up fig. 12 below), the plurality of conductive lines (12) on a same level and along a same direction (fig 1); a second ILD(upper portion of 36) (see marked up fig. 12 below)layer over the plurality of conductive lines and over the first ILD layer; a first conductive via (left via [col. 9 lines 35-55]) (see marked up fig. 12 below) in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines (12)(fig. 12), the first conductive via having a straight edge (fig. 1 and fig 12); and a second conductive via (right via[col. 9 lines 35-55] ) (see marked up fig. 12 below) in a second opening in the second ILD layer, the second conductive via in contact with a second (right 12) one of the plurality of conductive lines (fig. 12), the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines (left 12, right 12 in fig 12) , and the second conductive via having a straight edge (fig. 1 and fig 12), the straight edge of the second conductive via facing the straight edge of the first conductive via (fig. 12 and fig 1) a dielectric plug (upper portion of 36) (MPEP 2131 discloses “[t]he elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990)”) between and in contact with the straight edge of the first conductive via and the straight edge of the second conductive via (see marked up fig. 12 above), the dielectric plug along a direction orthogonal to the direction of the plurality of conductive lines (fig 12) the dielectric plug has an uppermost surface co-planar with an uppermost surface of the second ILD layer (fig 12)[ CMP used, col. 10 lines 1-10] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US Patent 10,020,223) as applied to claim 3 above in view of Xie et al. (US 2020/0343186) . Anderson et al. disclose the invention supra. Anderson et al. fails to disclose the dielectric plug tapers inwardly from a top of the dielectric plug to a bottom of the dielectric plug. Xie et al. the dielectric plug tapers inwardly (slopes)[0039] from a top of the dielectric plug to a bottom of the dielectric plug (502,602) (figs 6and 8). The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (tapering the dielectric plug), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (the bottom of the plug will take up less space) . 07-21-aia AIA Claim (s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US Patent 10,020,223) as applied to claim 8 above in view of Xie et al. (US 2020/0343186) . Anderson et al. disclose the invention supra. Anderson et al. fails to disclose the dielectric plug tapers inwardly from a top of the dielectric plug to a bottom of the dielectric plug. Xie et al. the dielectric plug tapers inwardly (slopes)[0039] from a top of the dielectric plug to a bottom of the dielectric plug (502,602) (figs 6and 8). The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (tapering the dielectric plug), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (the bottom of the plug will take up less space) . 07-21-aia AIA Claim (s) 15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US Patent 10,020,223) in view of Xie et al. (US 2020/0343186) . Regarding claim 15 Anderson et al. disclose a plurality of conductive lines (12)(fig. 12) in a first inter-layer dielectric (lower portion of 36) layer (see marked up fig. 12 below), the plurality of conductive lines (12) on a same level and along a same direction (fig 1); a second ILD(upper portion of 36) (see marked up fig. 12 below)layer over the plurality of conductive lines and over the first ILD layer; a first conductive via (left via [col. 9 lines 35-55]) (see marked up fig. 12 below) in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines (12)(fig. 12), the first conductive via having a straight edge in the plan view perspective (fig. 1); and a second conductive via (right via[col. 9 lines 35-55] ) (see marked up fig. 12 below) in a second opening in the second ILD layer, the second conductive via in contact with a second (right 12) one of the plurality of conductive lines (fig. 12), the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines (left 12, right 12 in fig 12) , and the second conductive via having a straight edge in the plan view perspective (fig. 1), the straight edge of the second conductive via facing toward the straight edge of the first conductive via (fig. 12 and fig 1). Jin fails to disclose a board; and a component coupled to the board, the component including an integrated circuit structure. Anderson et al. discloses a board (motherboard)[0050]; and a component coupled to the board, the component(integrated circuit chips)[0050] including an integrated circuit structure (integrated circuit chips)[0050]. The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (coupling the integrated circuit structure to a board), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (would allow the integrated circuit structure to communicate with the motherboard). Regarding claim 20, Xie et al. discloses the component is a packaged integrated circuit die (packaged form of integrated circuit chips)[0050] . 07-22-aia AIA Claim (s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US Patent 10,020,223) in view of Xie et al. (US 2020/0343186) as applied to claim 15 above and further in view of Meyers (US 2021/0287993) . Anderson et al.and Xie disclose the invention supra. Anderson et al. and Xie fail to disclose a memory coupled to the board. Meyers disclose a memory coupled (308) to the board (302)(fig. 12). The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (coupling the memory to a board), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (would allow the memory to communicate with the motherboard) . 07-22-aia AIA Claim (s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US Patent 10,020,223) in view of Xie et al. (US 2020/0343186) as applied to claim 15 above and further in view of Meyers (US 2021/0287993) . Anderson et al. and Xie disclose the invention supra. Anderson et al. and Xie fail to disclose a communication chip coupled to the board. Meyers disclose a communication chip (306A) coupled to the board (302)(fig. 12). The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (coupling the communication chip to a board), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (would allow the communication chip to communicate with the motherboard) . 07-22-aia AIA Claim (s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US Patent 10,020,223) in view of Xie et al. (US 2020/0343186) as applied to claim 15 above and further in view of Meyers (US 2021/0287993) . Anderson et al. and Xie disclose the invention supra. Anderson et al. and Xie fail to disclose a cammera coupled to the board. Meyers disclose a cammera (cammera) coupled to the board (302)(fig. 12). (The applicant’s specification fig 14 shows the same structure as Meyers fig 12) The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (coupling the cammera to a board), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (would allow the cammera to communicate with the motherboard) . 07-22-aia AIA Claim (s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US Patent 10,020,223) in view of Xie et al. (US 2020/0343186) as applied to claim 15 above and further in view of Meyers (US 2021/0287993) . Anderson et al. and Xie disclose the invention supra. Anderson et al. and Xie fail to disclose a battery coupled to the board. Meyers disclose a battery coupled to the board (302)(fig. 12). (The applicant’s specification fig 14 shows the same structure as Meyers fig 12) The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (coupling the battery to a board), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (would allow the battery to power the motherboard) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 21, 23, and 24 are allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 2, 6, 7, 9, 13, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRADLEY SMITH/Primary Examiner, Art Unit 2817 Application/Control Number: 17/956,775 Page 2 Art Unit: 2817 Application/Control Number: 17/956,775 Page 3 Art Unit: 2817 Application/Control Number: 17/956,775 Page 4 Art Unit: 2817 Application/Control Number: 17/956,775 Page 5 Art Unit: 2817 Application/Control Number: 17/956,775 Page 6 Art Unit: 2817 Application/Control Number: 17/956,775 Page 7 Art Unit: 2817 Application/Control Number: 17/956,775 Page 8 Art Unit: 2817 Application/Control Number: 17/956,775 Page 9 Art Unit: 2817 Application/Control Number: 17/956,775 Page 10 Art Unit: 2817 Application/Control Number: 17/956,775 Page 11 Art Unit: 2817 Application/Control Number: 17/956,775 Page 12 Art Unit: 2817
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