450DETAILED ACTION
Notice of Pre-AIA or AIA Status+
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 4 objected to because of the following informalities:
“a gate insulating cap layer is on the conductive structure” should be corrected to “a gate insulating cap layer on the conductive structure” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith et al. (U.S. Publication No. 20190058036 A1; hereinafter Smith) in view of Xie et al. (U.S. Publication No. 2017/0141211 A1; hereinafter Xie).
With respect to claim 1, Smith discloses an integrated circuit structure, comprising: a vertical stack of horizontal nanowires [421] over a first sub-fin (see Figure 4A); a gate structure [490] over the vertical stack of horizontal nanowires and on the first sub-fin (See Figure 4F); a dielectric structure [450/429] (filled with [453]) laterally spaced apart from the gate structure (see Figure 4F), wherein the dielectric structure is not over a channel structure but is on a second sub-fin (See ¶[0052-0054] Figure 4C, channel structures are removed to form recess [473] leaving adjacent “residual channel material” to the recess but not below); a dielectric gate cut plug [429] between the gate structure and the dielectric structure (See Figure 4F (Annotated below) and ¶[0053]; based on Applicant’s disclosure, the dielectric gate cut plug can be the same composition. Identical dielectric spacer structures [429] are found within the dielectric structure and adjacent the gate structure of Figure 4F).
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Smith fails to disclose a recess in the dielectric structure and in the dielectric gate cut plug; and a conductive structure in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.
In the same field of endeavor, Xie teaches a recess [137] in the dielectric structure and in the dielectric gate cut plug (see Figure 2S); and a conductive structure [150] in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure (see ¶[0049]; “Additionally, since there are conductive materials positioned within the SDB opening 137, i.e., the conductive materials 150, those conductive materials may serve other purposes, e.g., such as functioning as a local interconnect structure or line, while still not adversely affecting the isolating nature of the SDB isolation structure 162”). Implementation of a conductive material within the dielectric structure and dielectric cut plug would provide a local interconnect structure around the single diffusion break isolation structure of Xie (see Xie ¶[0049]) and Smith [450] (see Smith ¶[0048]) while maintaining the isolation of the SDB structure. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Smith and Xie discloses wherein the dielectric structure and the dielectric gate cut plug have a same composition (See Figure 4F; [429] found in both regions).
With respect to claim 3, the combination of Smith and Xie discloses a second gate structure over a second vertical stack of horizontal nanowires and on a third sub-fin, the second gate structure laterally spaced apart from the gate structure; and a second dielectric gate cut plug between the second gate structure and the dielectric structure (See Figure 4F).
With respect to claim 4, the combination of Smith and Xie discloses a gate insulating cap layer [627] is on the conductive structure and on the gate electrode of the gate structure (see Smith Figure 6).
With respect to claim 5, the combination of Smith and Xie discloses an epitaxial source or drain structure [431] at an end of the vertical stack of horizontal nanowires; and a conductive trench contact structure [433] on the epitaxial source or drain structure, the conductive trench contact structure electrically coupled to the conductive structure (see Smith ¶[0039]).
With respect to claim 6, Smith discloses an integrated circuit structure, comprising:
a fin [420] over a first sub-fin; a gate structure [490] over the fin (See Figure 4F); a dielectric structure [450/429] (filled with [453]) laterally spaced apart from the gate structure (see Figure 4F), wherein the dielectric structure is not over a channel structure but is on a second sub-fin (See ¶[0052-0054] Figure 4C, channel structures are removed to form recess [473] leaving adjacent “residual channel material” to the recess but not below); a dielectric gate cut plug [429] between the gate structure and the dielectric structure (See Figure 4F Annotated below and ¶[0053]; based on Applicant’s disclosure, the dielectric gate cut plug can be the same composition. Identical dielectric spacer structures [429] are found within the dielectric structure and adjacent the gate structure of Figure 4F).
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Smith fails to disclose a recess in the dielectric structure and in the dielectric gate cut plug; and a conductive structure in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.
In the same field of endeavor, Xie teaches a recess [137] in the dielectric structure and in the dielectric gate cut plug (See Figure 2S); and a conductive structure [150] in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure. (see ¶[0049]; “Additionally, since there are conductive materials positioned within the SDB opening 137, i.e., the conductive materials 150, those conductive materials may serve other purposes, e.g., such as functioning as a local interconnect structure or line, while still not adversely affecting the isolating nature of the SDB isolation structure 162”). Implementation of a conductive material within the dielectric structure and dielectric cut plug would provide a local interconnect structure around the single diffusion break isolation structure of Xie (see Xie ¶[0049]) and Smith [450] (see Smith ¶[0048]) while maintaining the isolation of the SDB structure. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 7, the combination of Smith and Xie discloses wherein the dielectric structure and the dielectric gate cut plug have a same composition (See Figure 4F; [429] found in both regions).
With respect to claim 8, the combination of Smith and Xie discloses a second gate structure over a second fin, the second fin on a third sub-fin, and the second gate structure laterally spaced apart from the gate structure; and a second dielectric gate cut plug between the second gate structure and the dielectric structure (See Figure 4F).
With respect to claim 9, the combination of Smith and Xie discloses a gate insulating cap layer [627] is on the conductive structure and on the gate electrode of the gate structure (see Smith Figure 6).
With respect to claim 10, the combination of Smith and Xie discloses an epitaxial source or drain structure [431] at an end of the fin; and a conductive trench contact structure [433] on the epitaxial source or drain structure, the conductive trench contact structure electrically coupled to the conductive structure (see Smith ¶[0039]).
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Hong et al. (U.S. Publication No. 2022/0336473 A1; hereinafter Hong) in view of Smith and Xie.
With respect to claim 11, Hong discloses a computing device, comprising: a board [105]; and a component [10] coupled to the board, the component including an integrated circuit structure (see Figure 1). Hong fails to disclose an integrated circuit structure comprising: a vertical stack of horizontal nanowires over a first sub-fin; a gate structure over the vertical stack of horizontal nanowires and on the first sub-fin; a dielectric structure laterally spaced apart from the gate structure, wherein the dielectric structure is not over a channel structure but is on a second sub-fin; a dielectric gate cut plug between the gate structure and the dielectric structure; a recess in the dielectric structure and in the dielectric gate cut plug; and a conductive structure in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.
In the same field of endeavor, Smith discloses an integrated circuit structure, comprising: a vertical stack of horizontal nanowires [421] over a first sub-fin (see Figure 4A); a gate structure [490] over the vertical stack of horizontal nanowires and on the first sub-fin (See Figure 4F); a dielectric structure [450/429] (filled with [453]) laterally spaced apart from the gate structure (see Figure 4F), wherein the dielectric structure is not over a channel structure but is on a second sub-fin (See ¶[0052-0054] Figure 4C, channel structures are removed to form recess [473] leaving adjacent “residual channel material” to the recess but not below); a dielectric gate cut plug [429] between the gate structure and the dielectric structure (See Figure 4F (Annotated below) and ¶[0053]; based on Applicant’s disclosure, the dielectric gate cut plug can be the same composition. Identical dielectric spacer structures [429] are found within the dielectric structure and adjacent the gate structure of Figure 4F).
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Furthermore in the same field of endeavor, Xie teaches a recess [137] in the dielectric structure and in the dielectric gate cut plug (see Figure 2S); and a conductive structure [150] in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure (see ¶[0049]; “Additionally, since there are conductive materials positioned within the SDB opening 137, i.e., the conductive materials 150, those conductive materials may serve other purposes, e.g., such as functioning as a local interconnect structure or line, while still not adversely affecting the isolating nature of the SDB isolation structure 162”). Integration of the integrated circuit structure of Smith results in the utilization of a single diffusion break, allowing for increased density and shrunken line-widths (See Smith ¶[0019]). Additionally, implementation of a conductive material within the dielectric structure and dielectric cut plug would provide a local interconnect structure around the single diffusion break isolation structure of Xie (see Xie ¶[0049]) and Smith [450] (see Smith ¶[0048]) while maintaining the isolation of the SDB structure. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 12, the combination of Hong, Smith and Xie discloses a memory [720] coupled to the board (see Hong Figure 7 and ¶[0095]).
With respect to claim 13, the combination of Hong, Smith and Xie discloses a communication chip [710] coupled to the board (see Hong ¶[0095]).
With respect to claim 14, the combination of Hong, Smith and Xie discloses wherein the component is a packaged integrated circuit die (See Hong ¶[0096]).
With respect to claim 15, the combination of Hong, Smith and Xie discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (see Hong ¶[0006] and ¶[0096]; SDB structures within logic circuits).
With respect to claim 16, Hong discloses a computing device, comprising: a board [105]; and a component [10] coupled to the board, the component including an integrated circuit structure (see Figure 1). Hong fails to disclose an integrated circuit structure, comprising: a fin over a first sub-fin; a gate structure over the fin; a dielectric structure laterally spaced apart from the gate structure, wherein the dielectric structure is not over a channel structure but is on a second sub-fin; a dielectric gate cut plug between the gate structure and the dielectric structure; a recess in the dielectric structure and in the dielectric gate cut plug; and a conductive structure in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.
In the same field of endeavor, Smith discloses an integrated circuit structure, comprising: a fin [420] over a first sub-fin; a gate structure [490] over the fin (See Figure 4F); a dielectric structure [450/429] (filled with [453]) laterally spaced apart from the gate structure (see Figure 4F), wherein the dielectric structure is not over a channel structure but is on a second sub-fin (See ¶[0052-0054] Figure 4C, channel structures are removed to form recess [473] leaving adjacent “residual channel material” to the recess but not below); a dielectric gate cut plug [429] between the gate structure and the dielectric structure (See Figure 4F Annotated below and ¶[0053]; based on Applicant’s disclosure, the dielectric gate cut plug can be the same composition. Identical dielectric spacer structures [429] are found within the dielectric structure and adjacent the gate structure of Figure 4F).
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Furthermore in the same field of endeavor, Xie teaches a recess [137] in the dielectric structure and in the dielectric gate cut plug (See Figure 2S); and a conductive structure [150] in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure. (see ¶[0049]; “Additionally, since there are conductive materials positioned within the SDB opening 137, i.e., the conductive materials 150, those conductive materials may serve other purposes, e.g., such as functioning as a local interconnect structure or line, while still not adversely affecting the isolating nature of the SDB isolation structure 162”). Integration of the integrated circuit structure of Smith results in the utilization of a single diffusion break, allowing for increased density and shrunken line-widths (See Smith ¶[0019]). Additionally, implementation of a conductive material within the dielectric structure and dielectric cut plug would provide a local interconnect structure around the single diffusion break isolation structure of Xie (see Xie ¶[0049]) and Smith [450] (see Smith ¶[0048]) while maintaining the isolation of the SDB structure. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 17, the combination of Hong, Smith and Xie discloses a memory [720] coupled to the board (see Hong Figure 7 and ¶[0095]).
With respect to claim 18, the combination of Hong, Smith and Xie discloses a communication chip [710] coupled to the board (see Hong ¶[0095]).
With respect to claim 19, the combination of Hong, Smith and Xie discloses wherein the component is a packaged integrated circuit die (See Hong ¶[0096]).
With respect to claim 20, the combination of Hong, Smith and Xie discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (see Hong ¶[0006] and ¶[0096]; SDB structures within logic circuits).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818