Prosecution Insights
Last updated: April 19, 2026
Application No. 17/957,003

HIGH SURFACE AREA CAPACITOR IN AN ELECTRONIC SUBSTRATE PACKAGE

Non-Final OA §103
Filed
Sep 30, 2022
Examiner
PARTHASARATHY, ROHIT
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
21 granted / 23 resolved
+23.3% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
31 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
56.6%
+16.6% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 23 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a) because they fail to show el. 111 as described in the specification in Para. [0017]. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: In Para. [0020], the word peeks is misspelled. In Para. [0028], Applicant refers to Figs. 2A and 2B, but seems to be referencing Fig. 4. Appropriate correction is required. Claim Objections Claim 25 is objected to because of the following informalities: the claim states in part “…wherein forming the dielectric layer comprising…”. Comprising should be comprises. Appropriate correction is required. Election/Restrictions Applicant’s election without traverse of Species A and Subspecies A2 in the reply filed on 1/28/2026 is acknowledged. Applicant withdraws claims 8-9, 11, 18 and 24 as being drawn to an unelected species. Claims 12-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species C, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/28/2026. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US20190057949A1 (Hwang) in view of US20200258682A1 (Matsuo). Regarding Claims 1 and 6, Hwang discloses a microelectronics package (Figs. 1 and 2, el. 1, Para. [0016]) comprising a first electrode material (Fig. 2, el. 530, Para. [0016]) having a first electrode surface (see annotated Fig. 2 below), the first electrode surface defining a plurality of first electrode peaks and first electrode valleys (see annotated Fig. 2 below); a second electrode (Fig. 2, el. 510, Para. [0016]) having a second electrode surface, the second electrode surface defining a plurality of second electrode peaks and second electrode valleys complementary to the first electrode peaks and first electrode valleys (see annotated Fig. 2 below), and a die (Fig. 1, el. 200, Para. [0016]) attached to the second electrode material (Fig. 2 el. 510, Para. [0031]); and a die (Fig. 1, el. 200, Para. [0016]) attached to the second electrode material (see annotated Fig. 2 below). Hwang does not disclose a continuous conductive material located at the first electrode peaks, PNG media_image1.png 652 636 media_image1.png Greyscale Matsuo discloses a capacitor (Figs. 1-10, el. 1, Para. [0030]) comprising: a first electrode material (Fig. 4, el. CS, Para. [0030]) with a plurality of first electrode peaks and first electrode valleys (see annotated Fig. 4 below, Para. [0061]); a second electrode (Fig. 4, el. 20b, Para. [0062]) having a second electrode surface (see annotated Fig. 4 below), the second electrode surface defining a plurality of second electrode peaks and second electrode valleys complementary to the plurality of first electrode peaks and first electrode valleys (see annotated Fig. 4 below); and a continuous conductive material located at the first electrode peaks (Fig. 4, el. 20a, Paras. [0050] and [0051]). PNG media_image2.png 757 654 media_image2.png Greyscale It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Hwang by adding a continuous conductive layer on the first electrode, as disclosed by Hwang. As implied by Matsuo, adding a conductive layer over the first electrode can improve conductivity, especially if the first electrode is of a low conductivity material (Matsuo, Para. [0055]). Regarding Claim 2, Hwang in view of Matsuo discloses the microelectronics package of claim 1, wherein the first electrode material is an anode material (Hwang discloses a capacitor 500 – see Para. [0016], where the first electrode 530 can be taken as the anode) and the second electrode material is a cathode material (the second electrode 510 of Hwang can be taken as the cathode). Regarding Claim 3, Hwang in view of Matuo discloses the microelectronics package of claim 2, further comprising a dielectric material located in between the anode material and the cathode material (Hwang, Fig. 2, el. 520, Para. Para. [0016]). Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Matsuo. Regarding Claim 10, Hwang in view of Matsuo discloses the microelectronics package of Claim 1, wherein the second electrode peaks have a height between 2um to 100um (Hwang, Para. [0032]. Hwang in view of Matsuo does not disclose that the first electrode peaks have a height between 2um to 100um. However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to make the first electrode peaks the same height as the second electrode peaks, as this would create a symmetrical capacitor structure, which is also shown in Fig. 2 of Hwang. Claims 19-21 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over US20080003768A1 (Oh) in view of Hwang. Regarding Claim 19, Oh discloses a method of manufacturing a substrate for a microelectronics package (Figs. 1-5, Para. [0016]), the method comprising: forming a plurality of first electrode peaks and first electrode valleys in a first electrode material (Fig. 2, Para. [0027]); depositing a conductive material onto the first electrode peaks and first electrode valleys (Fig. 3, Para. [0032]); forming a dielectric layer on the conductive material (Fig. 4, Para. [0036]); forming a plurality of second electrode peaks and second electrode valleys complementary to the first electrode peaks and first electrode valleys in a second electrode material (Fig. 5, Para. [0042]). Oh does not disclose the step of attaching a die to the second electrode material. Hwang discloses the step of attaching a die to a second electrode material (see Figs. 1 and 2 of Hwang, where the die 200 is attached to the second electrode material through pad 200a_ It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the method of Oh by adding the step of attaching a die, as disclosed by Hwang. As disclosed by Hwang, forming a capacitor this way and attaching it to a die overcomes limitations of making a die with a capacitor (Hwang, Para. [0003]). Regarding Claim 20, Oh in view of Hwang discloses the method of claim 19, wherein, forming the plurality of first electrode peaks and first electrode valleys in the first electrode material comprises forming the plurality of first electrode peaks and first electrode valleys in an anode material (Oh, Para. [0018] – which discloses that a capacitor is formed, and so the first electrode 630 can be taken as an anode); and forming the plurality of second electrode peaks and second electrode valleys in the second electrode material comprises forming the plurality of second electrode peaks and second electrode valleys in a cathode material (Oh, Para. [0018] – which discloses that a capacitor is formed, and so the second electrode 850 can be taken as an anode). Regarding Claim 21, Hwang in view of Matsuo discloses the method of claim 19, wherein depositing the conductive material onto the first electrode peaks and first electrode valleys comprises depositing the conductive material in a continuous pattern onto the first electrode peaks and first electrode valleys (Hwang, Fig. 4, Para. [0033]). Regarding Claim 25, Hwang in view of Matsuo discloses the method of claim 19, wherein forming the dielectric layer comprises forming an oxide layer on the conductive material (Hwang, Para. [0036]). Allowable Subject Matter 21. Claims 4-5, 7, 22, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 4, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination the limitation “…further comprising conductive particles dispersed throughout the first electrode material.” Regarding Claim 5, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination the limitation “…wherein the first electrode material is a conductive polymer material.” Regarding Claim 7, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination the limitation “…wherein the conductive material comprises nanoparticles.” Regarding Claim 22, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination the limitation “wherein depositing the conductive material comprises depositing aluminum via an aluminum sputter deposition process.” Regarding Claim 23, none of the prior art of record teaches, suggests or renders obvious, either alone or in combination the limitation “forming the plurality of first electrode peaks…comprises dry etching a surface of the first electrode material.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Sep 30, 2022
Application Filed
May 03, 2023
Response after Non-Final Action
Mar 04, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+13.3%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 23 resolved cases by this examiner. Grant probability derived from career allow rate.

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