DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-12, 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al (US Publication No. 2022/0415888) in view of Wen et al (US Publication No. 2019/0157159).
Regarding claim 1,Hsieh discloses an integrated circuit comprising: a first semiconductor device comprising (i) a first source region, (ii) a first drain region, (iii) a first body comprising semiconductor material extending in a first direction from the first source region to the first drain region Fig 6B, Fig 9-1,9-2,9-3, (iv) a first sub-fin below the first body, Fig 6B, Fig 9-1,9-2,9-3 and (v) a first gate structure Fig 6B, Fig 9-1 or 9-2, 346/222/226 extending in a second direction and on the first body Fig 9-1 or 9-2; a second semiconductor device comprising (i) a second source region, (ii) a second drain region, (iii) a second body comprising semiconductor material extending in the first direction from the second source region to the second drain region, (iv) a second sub-fin below the second body, and (v) a second gate structure extending in the second direction and on the second body Fig 9-1 or 9-2m and 1M-1; a gate cut laterally between and separating the first gate structure and the second gate structure Fig 9-1 or 9-2m and 1M-1, the gate cut Fig 6B, Fig 9-1, 210 comprising a first dielectric material ¶0088; a second dielectric material Fig 6B, Fig 9-1, 121 that is laterally between the first and second sub-fins, and a third dielectric material Fig 6B, Fig 9-1, 130 that is (i) laterally between the first and second sub-fins and (i) above the second dielectric material; wherein the gate cut is above the third dielectric material Fig 6B, Fig 9-1. Hsieh discloses all the limitations but silent on the arrangement of the gate cut structure. Whereas Wen discloses the gate cut comprising a first dielectric material Fig 13, 114 and extending along an entire height of the first gate structure Fig 13, 112 and the second gate structure Fig 13, 112; a second dielectric material Fig 13, 105 that is laterally between the first and second sub-fins, and a third dielectric material Fig 13, 106 that is (i) laterally between the first and second sub-fins and (i) above the second dielectric material Fig 13, 105; wherein the gate cut is directly on the third dielectric material Fig 13, 106 and has a bottommost surface that is above a top surface of the second dielectric material Fig 13, 105. Hsieh and Wen are analogous art because they are directed to semiconductor devices having gate cut structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Wen as an alternative arrangement known in the art to improve device performance.
Regarding claim 2, Hsieh discloses wherein an interface is between the second dielectric material and the third dielectric material Fig 9-1.
Regarding claim 3, Hsieh discloses wherein the interface is a seam or a grain boundary Fig 6B, Fig 9-1.
Regarding claim 4,Hsieh discloses wherein the second dielectric material and the third dielectric material are compositionally different ¶0053.
Regarding claim 5, Hsieh discloses wherein the second dielectric material and the third dielectric material are elementally the same ¶0048, 0053-0055.
Regarding claim 6,Hsieh discloses wherein the gate cut extends within, but not through, the third dielectric material Fig 6B.
Regarding claim 8,Hsieh discloses wherein the third dielectric material comprises silicon and one or more of oxygen, nitrogen, or carbon ¶0054.
Regarding claim 9,Hsieh discloses wherein the second dielectric material comprises silicon and one or more of oxygen, nitrogen, or carbon¶0048.
Regarding claim 10,Hsieh discloses a substrate that is below the sub-fin and below the third dielectric material Fig 6B, Fig 9-1.
Regarding claim 11,Hsieh discloses wherein the second dielectric material has a first height and the third dielectric material has a second heights, the first and second heights measured in a vertical direction orthogonal to both the first and second directions, wherein the first height is greater than the second height by at least 10% Fig 6B, Fig 9-1.
Regarding claim 12,Hsieh discloses wherein the first gate structure wraps at least in part around at least a section of the first body, and the first body is one of a nanoribbon, a nanosheet, a nanowire, or a fin Fig 6B, Fig 9-1, 9-2, 9-3.
Regarding claim 15, Hsieh discloses an integrated circuit comprising: a first sub-fin Fig 6B, Fig 9-1,9-2,9-3, and a first gate structure above the first sub-fin Fig 6B, Fig 9-1 or 9-2, 346/222/226; a second sub-fin Fig 6B, Fig 9-1 or 9-2, and a second gate structure Fig 6B, Fig 9-1 or 9-2, 346/222/226 above the second sub-fin; a gate cut laterally between the first and second gate structures, the gate cut Fig 6B, Fig 9-1, 210 comprising a first dielectric material¶0088; a second dielectric material Fig 6B, Fig 9-1, 121 laterally between the first and second sub-fins; and an etch stop layer that is between the second dielectric material and the gate cut Fig 6B, Fig 9-1, 130. Hsieh discloses all the limitations but silent on the arrangement of the gate cut structure. Whereas Wen discloses the gate cut comprising a first dielectric material Fig 13, 114 and extending along an entire height of the first gate structure and the second gate structure Fig 13, 112;a second dielectric material Fig 13, 105 laterally between the first and second sub-fins; and an etch stop layer Fig 13, 106 that is between the second dielectric material and the gate cut Fig 13, 114e wherein the gate cut is directly on the etch stop layer Fig 13, 106. Hsieh and Wen are analogous art because they are directed to semiconductor devices having gate cut structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Wen as an alternative arrangement known in the art to improve device performance.
Regarding claim 16, Hsieh discloses wherein the etch stop layer comprises a third dielectric material, with an interface between the second dielectric material and the third dielectric material of the etch stop layer Fig 6B, Fig 9-1.
Regarding claim 17, Hsieh discloses wherein the etch stop layer is in contact with each of the first gate structure and the second gate structure Fig 6B, Fig 9-1.
Regarding claim 18, Hsieh discloses wherein the first gate structure comprises gate dielectric that is on at least a section of an upper surface of the etch stop layer, a gate electrode Fig 6B, Fig 8J-1, Fig 9-1.
Claims13-14, 19-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al (US Publication No. 2022/0415888) and Wen et al (US Publication No. 2019/0157159) and in further view of Motoyama et al (US Publication No. 2024/0112986).
Regarding claim 13, Hsieh discloses all the limitations but silent on the type of channel region. Whereas Motoyoma discloses a vertical stack of a plurality of bodies comprising semiconductor material extending in the first direction from the first source region to the first drain region, the plurality of bodies includes the first body, and the plurality of bodies comprises a plurality of nanoribbons, nanowires, or nanosheets Fig 17. Hsieh and Motoyama are analogous art because they are directed to semiconductor devices having gate cut structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Motoyama as an alternative channel arrangement known in the art to improve device performance.
Regarding claim 14, Motoyama discloses a printed circuit board comprising the integrated circuit of claim 1 ¶0062.
Regarding claim 19, Hsieh discloses an integrated circuit comprising: a first sub-fin Fig 6B, Fig 9-1,9-2,9-3, and a first gate structure Fig 6B, Fig 9-1 or 9-2, 346/222/226 above the first sub-fin; a second sub-fin Fig 6B, Fig 9-1 or 9-2, , and a second gate structure Fig 6B, Fig 9-1 or 9-2, 346/222/226 above the second sub-fin; a structure Fig 6B, Fig 9-1, 210 laterally between and separating the first and second gate structures, the structure comprising a first dielectric material ¶0088; a second dielectric material Fig 6B, Fig 9-1, 130 laterally between the first and second sub-fins, the structure landing on the second dielectric material Fig 6B, Fig 9-1, 130; and a fourth dielectric material Fig 6B, Fig 9-1, 121 and that is below the first and second sub-fins; wherein the second dielectric material is compositionally distinct from the first dielectric material and the fourth dielectric material ¶0058. Hsieh discloses all the limitations but silent on the backside interconnect structure. Whereas Motoyama discloses a backside interconnect structure comprising a dielectric material that is below the first and second sub fins Fig 17. Hsieh and Motoyama are analogous art because they are directed to semiconductor devices having gate cut structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Motoyama to improve connectivity.
Hsieh discloses all the limitations but silent on the arrangement of the gate cut structure. Whereas Wen discloses the structure comprising a first dielectric material Fig 13, 114 and extending along an entire height of the first gate structure and the second gate structure Fig 13, 112; a second dielectric material Fig 13, 106 laterally between the first and second sub-fins, the bottommost surface of the structure landing on the second dielectric material Fig 13, 106; a third dielectric material Fig 13, 105 laterally between the first and second sub-fins and below the second dielectric material Fig 13, 106. Hsieh and Wen are analogous art because they are directed to semiconductor devices having gate cut structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hsieh and incorporate the teachings of Wen as an alternative arrangement known in the art to improve device performance.
Regarding claim 20, Hsieh discloses wherein the structure extends within, but not through, the second dielectric material Fig 6B.
Regarding claim 21, Motoyama in view of Hsieh disclose wherein an interface extends laterally between a top surface of the backside interconnect structure and both (i) bottom surfaces of the first and second sub-fins and (ii) a bottom surface of the second dielectric material Fig 11 and Fig 17.
Regarding claim 22, Wen discloses wherein the second dielectric material is compositionally distinct from the fourth dielectric material ¶0016-0018.
Regarding claim 23, Hsieh discloses wherein the second dielectric material has a first height and the third dielectric material has a second height, the first and second heights measured in a vertical direction orthogonal to both the first and second directions, wherein the second height is greater than the first height by at least 10% Fig 6B, Fig 9-1,9-2,9-3. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the height, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ (CCPA 1980).
Response to Arguments
Applicant’s arguments with respect to claims 1-6, 8-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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