DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 8/12/2025. Claims 1-14 are pending in this application.
Claims 1, 3, 5-6, and 10-12 are amended.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 6/10/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al. (US 2020/0294998; hereinafter ‘Lilak’).
Regarding claim 1, Lilak teaches a semiconductor device (FIG. 1A, [0013]) comprising:
at least one pair of stacked semiconductor sheets for channel regions (116A and 116B used as channel; hereinafter referred to as ‘116AB’), each of the at least one pair of stacked semiconductor sheets has an inserted dielectric (106 is silicon nitride, silicon oxide, [0027]) present between the semiconductor sheets (shown in FIG. 1A); and
a gate structure (120A, 120B, 122A, 122B; hereinafter referred to as ‘GSAB’) encapsulating the at least one pair of stacked semiconductor sheets (GSAB encapsulating 116AB), wherein the gate structure is in direct contact (shown in FIG. 1A) with a lower surface of a lower semiconductor sheet in at least one pair of stacked semiconductor sheets (a lower surface of 116A), and is in direct contact (shown in FIG. 1A) with an upper surface of an upper semiconductor sheet in the at least one pair of semiconductor sheets (a upper surface of 116B).
Regarding claim 1 (alternative mapping for claim 2), Lilak teaches a semiconductor device (FIG. 1A, [0013]) comprising:
at least one pair of stacked semiconductor sheets for channel regions (two vertically stacked 116A at the lower left used as channel; hereinafter referred to as ‘116AA’), each of the at least one pair of stacked semiconductor sheets has an inserted dielectric (122A) present between the semiconductor sheets (shown in FIG. 1A); and
a gate structure (120A and 122A; hereinafter referred to as ‘GSA’) encapsulating the at least one pair of stacked semiconductor sheets (GSA encapsulating 116AA), wherein the gate structure is in direct contact (shown in FIG. 1A) with a lower surface of a lower semiconductor sheet in at least one pair of stacked semiconductor sheets (a lower surface of the lower 116A), and is in direct contact (shown in FIG. 1A) with an upper surface of an upper semiconductor sheet in the at least one pair of semiconductor sheets (a upper surface of the upper 116A).
Regarding claim 2, Lilak teaches the semiconductor device of claim 1, wherein the inserted dielectric does not extend to an edge of semiconductor sheets (122A does not extend to an edge of 116A, FIG. 1A).
Regarding claim 3, Lilak teaches the semiconductor device of claim 1, wherein the at least one pair of stacked semiconductor sheets includes at least a first pair of semiconductor sheets (116A and 116B on the left side, FIG. 1A) and a second pair of semiconductor sheets (116A and 116B on the right side), wherein the gate structure is in direct contact (shown in FIG. 1A) with a lower surface of a lower semiconductor sheet in the second pair of stacked semiconductor sheets (a lower surface of 116A on the right side), and is in direct contact (shown in FIG. 1A) with an upper surface of an upper semiconductor sheet in the first pair of semiconductor sheets (a upper surface of 116B on the left side).
Regarding claim 4, Lilak teaches the semiconductor device of claim 1, wherein the at least one pair of stacked semiconductor sheets having the one inserted dielectric is a channel cluster (116A and 116B having 106 is a channel cluster, FIG. 1A; hereinafter referred to as CC’).
Regarding claim 5, Lilak teaches the semiconductor device of claim 4, wherein the gate structure includes a gate dielectric (122A and 122B, FIG. 1A, [0013]) that wraps around an exterior surface of the channel cluster (122A and 122B wraps around CC), and the gate structure includes a gate electrode (120A and 120B), in directed contact with the gate dielectric (shown in FIG. 1A).
Regarding claim 6, Lilak teaches a semiconductor device (FIG. 1A, [0013]) comprising:
at least one pair of stacked semiconductor sheets for channel regions (two vertically stacked 116A at the lower left used as channel; hereinafter referred to as ‘116AA’); and
a gate structure (120A and 122A over and below 1166AA; hereinafter referred to as ‘GSA’) including a gate dielectric (122A) and a gate electrode (120A), present on the channel region encapsulating each of the at least one pair of stacked semiconductor sheets (shown in FIG. 1A),
wherein the at least one pair of stacked semiconductor sheets has a space between the stacked semiconductor sheets (two vertically stacked 116A defined a space therebetween, and this space is entirely filled with 122A and 123A, [0019]) entirely filled with (shown in FIG. 1A) a dielectric material of the gate dielectric for the gate structure (122A) and an inner spacer (123A), and a portion of the gate electrode for the gate structure (a portion is filled with 120A) is present encapsulating an exterior of the at least one pair of stacked semiconductor sheets (the exterior of 116AA is encapsulated by 120A) having the space between the stacked sheets filled with the dielectric material (122A and 123A are dielectric materials, [0052]).
Regarding claim 8, Lilak teaches the semiconductor device of claim 6, wherein a channel cluster (116AA having the space is a channel cluster, FIG. 1A; hereinafter referred to as ‘CC2’) is provided by the at least one pair of stacked semiconductor sheets having the space between the stacked semiconductor sheets filled with the dielectric material of the gate dielectric (CC2 having the space that filled with 122A), wherein a portion of the gate dielectric having a conformal thickness is present on exterior surfaces of the channel cluster (122A are wrapped around CC2).
Regarding claim 9, Lilak teaches the semiconductor device of claim 6, wherein the dielectric material of the gate dielectric for the gate structure is comprised of a high-k dielectric material (112A is high-k gate dielectric materials, [0019]).
Claims 10 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 20180233572; hereinafter ‘Cheng’).
Regarding claim 10, Cheng teaches a semiconductor device (101, FIGS. 1a-1c, [0039]) comprising:
a channel region of stacked semiconductor layers (three vertically stacked 106 used as channel, FIGS. 1c; hereinafter referred to as ‘S106’) arranged in clusters (S106 arranged in clusters; hereinafter called ‘CC3’), wherein each cluster includes a pair of the semiconductor sheets (two vertically stacked 106) with dielectric material (1305) present entirely therebetween (shown in FIG. 1c);
a gate structure (1301 and one 1305 between 1301 and 106, FIG. 1b; hereinafter referred to as ‘GSCheng’) encapsulating the channel region of stacked semiconductor sheets arranged in clusters (shown in FIG. 1c), wherein a portion of the gate structure (1305 of GSCheng) is present between the clusters (shown in FIG. 1c); and
source and drain regions (900, 902, FIG. 1a, [0058]) present on opposing sides of the channel region (shown in FIG. 1a).
Regarding claim 13, Cheng teaches the semiconductor device of claim 10, wherein the dielectric material that is present between the pair of semiconductor sheets (1305 of S106) has a same composition (1305) as a composition of the gate dielectric of the gate structure (1305 of GSCheng).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 2020/0294998) in view of Chen et al. (US 2022/0310783; hereinafter Chen).
Regarding claim 7, Lilak teaches the semiconductor device of claim 6, but does not explicitly teach the semiconductor device further including a base dielectric isolation layer present between the at least one pair of stacked semiconductor sheets and a supporting substrate.
Chen teaches a semiconductor device (200, FIG. 3D, [0017]) further including a base dielectric isolation layer (204, [0020]) present between the at least one pair of stacked semiconductor sheets and a supporting substrate (204 present between 210A, 210B and 202, [0019]).
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Lilak to obtain and achieve the semiconductor device further including a base dielectric isolation layer present between the at least one pair of stacked semiconductor sheets and a supporting substrate as claimed, because an additional isolation layer beneath the semiconductor stack reduces parasitic capacitance and improves device performance [0014, 0038].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination with Lilak due to above reason.
Claim 11is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 20180233572) in view of Wu et al. (US 2021/0202323; hereinafter ‘Wu’).
Regarding claim 11, Cheng teaches the semiconductor device of claim 10, but does not explicitly teach the semiconductor device wherein the dielectric material that is present between the pair of semiconductor sheets has a different composition than a composition of a gate dielectric of the gate structure.
Wu teaches a semiconductor device (200, FIG. 3, [0017]) wherein the dielectric material that is present between the pair of semiconductor sheets (248 and 252 includes SiO2, SiON, [0023, 0031]) for has a different composition than a composition of a gate dielectric of the gate structure (254 is the channel insulating dielectric and including LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3, BaTiO3, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, (Ba,Sr)TiO3, Al2O3, HfSiO, LaSiO, AlSiO, FIG. 12, [0032])
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Cheng to obtain and achieve the semiconductor device wherein the dielectric material that is present between the pair of semiconductor sheets has a different composition than a composition of a gate dielectric of the gate structure as claimed, because the selecting different compositions for the channel-side dielectric and the gate dielectric is technically justified by their distinct functions-ow defect Si/oxide interface [0029, 0031] and thermal stability under anneal [0034-0037]. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu combination with Cheng due to above reason.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 20180233572) in view of Wu (US 2021/0202323), and further in view of Lilak (US 2020/0294998).
Regarding claim 12, Chen in view of Wu teaches the semiconductor device of claim 11, but does not explicitly teach the semiconductor device wherein the dielectric material that is present between the pair of semiconductor sheets has a portion that is laterally offset from an edge of the pair of semiconductor sheets.
Lilak teaches a semiconductor device (FIG. 1A, [0013]) wherein the dielectric material that is present between the pair of semiconductor sheets (122A and 123A that are positioned between the two vertically stacked 116A at the lower left used as channel) has a portion (122A) that is laterally offset from an edge of the pair of semiconductor sheets (shown in FIG. 1A).
As taught by Lilak, one of ordinary skill in the art would utilize and modify the above teaching into Cheng in view of Wu to obtain and achieve the semiconductor device wherein the dielectric material that is present between the pair of semiconductor sheets has a portion that is laterally offset from an edge of the pair of semiconductor sheets as claimed, because placing the dielectric as only a portion between the channel regions, rather than extending it fully to the channel edge, merely serves as a precautionary measure to ensure process margin and to provide alternative insulating coverage in case of potential defects [0019].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lilak in combination with Chen in view of Wu due to above reason
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 20180233572) in view of Chen et al. (US 2022/0310783).
Regarding claim 14, Cheng teaches the semiconductor device of claim 13, but does not explicitly teach the semiconductor device further including a base dielectric isolation layer present between a first of the clusters in the channel and a supporting substrate.
Chen teaches a semiconductor device (200, FIG. 3D, [0017]) further including a base dielectric isolation layer (204, [0020]) present between a first of the clusters in the channel and a supporting substrate (204 present between 210A, 210B and 202, [0019]).
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Cheng to obtain and achieve the semiconductor device further including a base dielectric isolation layer present between a first of the clusters in the channel and a supporting substrate as claimed, because an additional isolation layer beneath the semiconductor stack reduces parasitic capacitance and improves device performance [0014, 0038].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination with Cheng due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Claim 1
Applicant submits, in pages 19-20 of Remark, that “Lilak fails to teach or suggest at least each of the “at least one pair of stacked semiconductor sheets has an inserted dielectric present between the semiconductor sheets” … and there is no inserted dielectric between each of the at least one pair of the stacked semiconductor sheets in Lilak. Instead, in Lilak, there is an inserted dielectric between the pair itself”.
The examiner respectfully disagrees.
As described in Lilak [0013] and illustrate in FIG. 1A, semiconductor elements 116A and 116B are stacked structures, and dielectric isolation region 106 is explicitly disposed between these stacked semiconductor sheets. Isolation region 106 is a dielectric material and therefore meets the claim requirement that “at least one pair of stacked semiconductor sheets has an inserted dielectric present between the semiconductor sheets”.
Furthermore, the pending claim language does not specify and particular function, orientation, or type of the inserted dielectric beyond its presence “between the semiconductor sheets”. The claim does not exclude the dielectric from being an isolation region, nor does it require the dielectric to serve any specific operation role. Accordingly, Lilak’s disclosure of isolation region 106 positioned between stacked semiconductor sheets is sufficient to anticipate the claimed feature.
Claim 6
Applicant submits, in pages 20-21 of Remark, that “Lilak fails to teach or suggest at least “the at least one pair of stacked semiconductor sheets has a space between the stacked semiconductor sheets entirely filled with a dielectric material of the gate dielectric for the gate structure and an inner spacer” … Since there is a gate electrode (120A) between the semiconductor sheets”.
The examiner respectfully disagrees.
As described in Lilak [0013] and illustrate in FIG. 1A, semiconductor elements 116A and 116B are stacked structures in which the regions between the semiconductor sheets are filled with dielectric material, such as gate dielectric 122A and isolation dielectric 106. These dielectric materials extend between the semiconductor sheets, thereby satisfying the claim requirement that “the space between the stacked semiconductor sheets entirely filled with a dielectric material… and an inner spacer”.
Furthermore, the pending claim language does not exclude the presence of conductive material adjacent to the dielectric. It only requires that the space between the semiconductor sheets be filled with dielectric material of the gate dielectric and an inner spacer. Lilak’s disclosure of dielectric 122A and isolation region 106 between semiconductor sheets 116A and 116B is sufficient to satisfy this limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-6PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/EVA Y MONTALVO/Supervisory Patent Examiner, Art Unit 2818