DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/7/2026 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 6/29/2026. Claims 1-2, 4-25 are pending in this application. Claims 1, 6, 10-11, and 13 are amended. Claims 15-25 remain withdrawn.
Claim Objections
Claims 1, 7, and 14 are objected to because of the following informalities:
In claim 1, line 11, “that wraps around the second pair of dielectric sheets” should read --that wraps around the second pair of stacked semiconductor sheets-- (emphasis added).
In claim 7, line 1, “The semiconductor device of claim 6 further” should read --The semiconductor device of claim 6, further-- (emphasis added).
In claim 14, line 1, “The semiconductor device of claim 10 further” should read --The semiconductor device of claim 10, further-- and line 2, “a first of the vertical clusters in the channel” should read -- the first cluster of the channel region-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-7 and 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2019/0131395; hereinafter ‘Lee’).
Regarding claim 1, Lee teaches a semiconductor device (FIG. 13, [0074]) comprising:
at least one pair of stacked semiconductor sheets (vertically stacked semiconductor sheets including the second and third 14P’ and 14E from the bottom (hereinafter ‘14P’-2’ and ‘14P’-3) within pFET and the first and second 15P’ and 15E from the bottom (hereinafter ‘15P’-1’ and ‘15P’-2’) within nFET, see the annotations in FIG. 13, [0064]; hereinafter ‘14PS’ and ‘15PS’) for channel regions (portions of 14PS and 15PS positioned between 22S and 26S, [0050, 0053, 0072-0073]; hereinafter ‘CR’),
each of the at least one pair of stacked semiconductor sheets (14PS and 15PS) has an inserted dielectric (20, [0040]) present between the semiconductor sheets (20 present between 14P’-2 and 14P’-3; and 20 present between 15P’-2 and 15P’-2),
the inserted dielectric (20) being planar (as shown in FIG. 13) and directly contacts each of the at least one pair of stacked semiconductor sheets (the third portion of 20 from bottom (hereinafter ‘20-3’) directly contacting 14P’-2 and 14P’-3; and the fifth portion of 20 from bottom (hereinafter ‘20-5’) directly contacting 15P’-1 and 15P’-2, see the annotations in FIG. 13),
wherein the at least one pair of stacked semiconductor sheets (14PS and 15PS) includes a first pair of stacked semiconductor sheets (14PS) and a second pair of stacked semiconductor sheets (15PS) above the first pair of stacked semiconductor sheets (14PS above 15PS); and
a gate structure (a gate structure including gate dielectric material 32 and work function metal 34 corresponding to the gate electrode, [0065]; hereinafter ‘GS’) encapsulating the first pair of stacked semiconductor sheets (GS encapsulating 14PS by extending around each of 14P’-2 and 14P’-3 constituting 14PS) and encapsulating the second pair of stacked semiconductor sheets (GS encapsulating 15PS by extending around each of 15P’-1 and 15P’-2 constituting 15PS),
wherein the gate structure (GS) includes a gate dielectric (32) that wraps around the first pair of stacked semiconductor sheets (32 wraps around 14PS by extending around each of 14P’-2 and 14P’-3 constituting 14PS, since the gate cavity extends above, beneath and around each suspended semiconductor sheets, and 32 is formed on the physically exposed surfaces thereof, [0057, 0066]) and that wraps around the second pair of dielectric sheets (32 wraps around 15PS by extending around each of 15P’-1 and 15P’-2 constituting 15PS),
the gate dielectric (32) in direct contact with a lower surface of a lower semiconductor sheet of the second pair of stacked semiconductor sheets (32 directly contacting the lower surface of the lower semiconductor sheet 15P’-1 of 15PS, see the annotations in FIG. 13), and in direct contact with an upper surface of an upper semiconductor sheet of the first pair of stacked semiconductor sheets (32 directly contacting the upper surface of the upper semiconductor sheet 14P’-3 of 14PS, see the annotations in FIG. 13), and
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wherein the gate structure (GS) includes a gate electrode (34) between the gate dielectric in direct contact with the lower surface of the lower semiconductor sheet of the second pair of stacked semiconductor sheets and the gate dielectric in direct contact with the upper surface of the upper semiconductor sheet of the first pair of stacked semiconductor sheet (the fourth portion of 34 from the bottom (hereinafter ‘34-4’) is present between the fourth 32 from the bottom (hereinafter ‘32-4’) directly contacting the lower surface of 15P’-1 of 15PS and 32-4 directly contacting the upper surface of 14P’-3, see the annotations in FIG. 13).
Regarding claim 2, Lee teaches the semiconductor device of claim 1, wherein the inserted dielectric does not extend to an edge of semiconductor sheets (20 does not extend to an edge of 14P’-2, 14P’-3, 15P’-1, and 15P’-2, FIG. 13).
Regarding claim 4, Lee teaches the semiconductor device of claim 1, wherein the at least one pair of stacked semiconductor sheets having the one inserted dielectric is a channel cluster (14PS and 15PS including 20 correspond to the channel clusters because they function as the respective channels of the pFET and nFET devices, FIG. 13, [0072-0073]; hereinafter ‘CR14PS’ and ‘CR15PS’).
Regarding claim 5, Lee teaches the semiconductor device of claim 4, wherein the gate dielectric wraps around an exterior surface of the channel cluster (32 wraps around CR14PS and CR15PS by extending around each of 14P’-2 and 14P’-3 constituting CR14PS and each of 15P’-1 and 15P’-2 constituting CR15PS, since the gate cavity extends above, beneath and around each suspended semiconductor sheet, and 32 is formed on the physically exposed surfaces thereof, [0057, 0066]), and the gate electrode is in direct contact with the gate dielectric (34 directly contacting with 32, FIG. 13).
Regarding claim 6, Lee teaches a semiconductor device (FIG. 13, [0074]) comprising:
at least one pair of stacked semiconductor sheets (vertically stacked semiconductor sheets including the second and third semiconductor sheets from the bottom, each including portions 14P’ and 14E (hereinafter ‘14P’-2’ and ‘14P’-3) within pFET and the first and second semiconductor sheets from the bottom, each including portions 15P’ and 15E (hereinafter ‘15P’-1’ and ‘15P’-2’) within nFET, see the annotations in FIG. 13, [0064]; hereinafter ‘14PS’ and ‘15PS’) for a channel region (portions of 14PS and 15PS positioned between 22S and 26S, [0050, 0053, 0072-0073]; hereinafter ‘CR’),
wherein the at least one pair of stacked semiconductor sheets (14PS and 15PS) includes at least a first pair of stacked semiconductor sheets (14PS) and a second pair of stacked semiconductor sheets (15PS) above the first pair of stacked semiconductor sheets (15PS above 14PS, FIG. 13); and
a gate structure (a gate structure including gate dielectric material 32 and work function metal 34 corresponding to the gate electrode, [0065]; hereinafter ‘GS’)
including a gate dielectric (32) and a gate electrode (34) present on the channel region (32 and 34 present on CR, FIG. 13)
encapsulating the first pair of stacked semiconductor sheets (GS encapsulating 14PS by extending around each of 14P’-2 and 14P’-3 constituting 14PS) and encapsulating the second pair of stacked semiconductor sheets (GS encapsulating 15PS by extending around each of 15P’-1 and 15P’-2 constituting 15PS),
wherein the gate dielectric (32) wraps around the first pair of stacked semiconductor sheets (32 wraps around 14PS by extending around each of 14P’-2 and 14P’-3 constituting 14PS, since the gate cavity extends above, beneath and around each suspended semiconductor sheet, and 32 is formed on the physically exposed surfaces thereof, [0057, 0066]) and wraps around the second pair of stacked semiconductor sheets (32 wraps around 15PS by extending around each of 15P’-1 and 15P’-2 constituting 15PS), and
wherein the gate dielectric (32) is in direct contact with a lower surface of a lower semiconductor sheet of the second pair of stacked semiconductor sheets (32 directly contacting the lower surface of the lower semiconductor sheet 15P’-1 of 15PS, FIG. 13), and is in direct contact with an upper surface of an upper semiconductor sheet of the first pair of stacked semiconductor sheets (32 directly contacting the upper surface of the upper semiconductor sheet 14P’-3 of 14PS, FIG. 13),
wherein the at least one pair of stacked semiconductor sheets (14PS and 15PS) has a space (a space defined by the regions occupied by the third and fifth portions of 32 from the bottom (hereinafter ‘32-3’ and ‘32-5’) and the third and fifth portions of 20 from the bottom (hereinafter ‘20-3’ and ‘20-5’), see the annotated regions in FIG. 13, [0040]; hereinafter ‘S’) between the stacked semiconductor sheets (S between 14P'-2 and 14P’-3 of 14PS and 15P’-1 and 15P’-2 of 15PS) entirely filled with a dielectric material of the gate dielectric for the gate structure and an inner spacer (S is entirely filled with 32 of GS and 20), and
Note: The phrase “a space” is interpreted as requiring at least one space between the stacked semiconductor sheets of at least one pair that is entirely filled with dielectric material, rather than requiring the entirety of every intervening region between the stacked semiconductor sheets to be entirely filled with dielectric material.
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a portion of the gate electrode for the gate structure (a portion of 34 for GS disposed between 24, see the annotation in FIG. 13, [0052]; hereinafter ‘34P’) is present between the gate dielectric in direct contact with the upper surface of the upper semiconductor sheet of the first pair of stacked semiconductor sheets and the gate dielectric in direct contact with the lower surface of the lower semiconductor sheet of the second pair of stacked semiconductor sheet (34P is present between the fourth 32 from the bottom (hereinafter ’32-4’) directly contacting the upper surface of 14P’-3 of 14PS and 32-4 directly contacting the lower surface of 15P’-1, see the annotated region in FIG. 13).
Regarding claim 7, Lee teaches the semiconductor device of claim 6 further including a base dielectric isolation layer (11, FIG. 13, [0040]) present between the at least one pair of stacked semiconductor sheets and a supporting substrate (10, [0025]; 11 present between 14PS and 10).
Regarding claim 9, Lee teaches the semiconductor device of claim 6, wherein the dielectric material of the gate dielectric for the gate structure is comprised of a high-k dielectric material (32 is a high-k dielectric material, [0067]).
Regarding claim 10, Lee teaches a semiconductor device (FIG. 13, [0074]) comprising:
a channel region of stacked semiconductor layers (portions of vertically stacked semiconductor sheets including 14P’ and 14E within pFET (hereinafter ‘14PS’) and 15P’and 15E within nFET (hereinafter ‘15PS’) positioned between 22S and 26S, see the annotations in FIG. 13, [0050, 0053, 0060, 0064, 0072-0073]; hereinafter ‘CR14PS’ and ‘CR15PS’) arranged in vertical clusters (CR14PS and CR15PS arranged in vertical clusters) that includes a first cluster (CR14PS) and a second cluster (CR15PS) above the first cluster (CR15PS above CR14PS, FIG. 13),
wherein each cluster of the vertical clusters (CR14PS and CR15PS) includes a pair of semiconductor sheets (the second and third semiconductor sheets from the bottom, each including portions 14P’ and 14E (hereinafter ‘14P’-2’ and ‘14P’-3) of CR14PS and the first and second semiconductor sheets from the bottom, each including portions 15P’ and 15E (hereinafter ‘15P’-1’ and ‘15P’-2’) of CR15PS) with dielectric material (a dielectric material including the third and fifth portions of 32 from the bottom (hereinafter ‘32-3’ and ‘32-5’) and the third and fifth portions of 20 from the bottom (hereinafter ‘20-3’ and ‘20-5’), [0040]; hereinafter ‘DM’) present entirely there between (32-3 and 20-3 of DM present entirely between 14P’-2 and 14P’-3; and 32-5 and 20-5 of DM present entirely between 15P’-1 and 15P’-2, see the annotations in FIG. 13);
a gate structure (a gate structure including gate dielectric material 32 and work function metal 34 corresponding to the gate electrode, [0065]; hereinafter ‘GS’) encapsulating the first cluster and the second cluster (GS encapsulating CR14PS by extending around each of 14P’-2 and 14P’-3 constituting CR14PS and encapsulating CR15PS by extending around each of 15P’-1 and 15P’-2 constituting CR15PS), wherein a portion of the gate structure (the fourth 34 from the bottom (hereinafter ‘34-4’) and the fourth 32 from the bottom (hereinafter ‘32-4’); hereinafter ‘34P’, see the annotations in FIG. 13) is present between the first cluster and the second cluster (34P is present between CR14PS and CR15PS), wherein the gate structure (GS) includes:
a gate dielectric (32) that wraps around the first cluster (32 wraps around CR14PS by extending around each of 14P’-2 and 14P’-3 constituting CR14PS, since the gate cavity extends above, beneath and around each suspended semiconductor sheet, and 32 is formed on the physically exposed surfaces thereof, [0057, 0066]) and wraps around the second cluster (32 wraps around CR15PS by extending around each of 15P’-1 and 15P’-2 constituting CR15PS),
wherein the gate dielectric (32) is in direct contact with a lower surface of a lower semiconductor sheet of the second cluster (32-4 directly contacting the lower surface of 15P’-1 of CR15PS, see the annotations in FIG. 13), and is in direct contact with an upper surface of an upper semiconductor sheet of the first cluster (32-4 directly contacting the upper surface of 14P’-3 of CR14PS, see the annotations in FIG. 13); and
a gate electrode (34) between the gate dielectric in direct contact with the upper surface of the upper semiconductor sheet of the first cluster and the gate dielectric in direct contact with the lower surface of the lower semiconductor sheet of the second cluster (34-4 between 32-4 directly contacting the upper surface of 14P’-3 of CR14PS and 32-4 directly contacting the lower surface of 15P’-1 of CR15PS, see the annotations in FIG. 13); and
source and drain regions (22S and 26S) present on opposing sides of the channel region (22S and 26S present on opposing sides of CR14PS and CR15PS).
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Note: The phrase “dielectric material present entirely there between” is interpreted as requiring each portion of dielectric material identified as corresponding to the claimed dielectric material to be located entirely between the respective pair of semiconductor sheets, rather than requiring the entire space between the semiconductor sheets to be completely filled with dielectric material.
Regarding claim 11, Lee teaches the semiconductor device of claim 10, wherein the dielectric material that is present between the pair of semiconductor sheets has a different composition than a composition of the gate dielectric (the composition of 20-3 and 20-5 of DM is different from that of 32 because 20 comprises silicon dioxide and 32 comprises a high-k material, such as HfO2, having a dielectric constant greater than that of silicon dioxide, [0038, 0045, 0067]).
Regarding claim 12, Lee teaches the semiconductor device of claim 11, wherein the dielectric material that is present between the pair of semiconductor sheets (DM) has a portion (a portion of each of 32-3 and 32-5; hereinafter ‘32P’) that is laterally offset from an edge of the pair of semiconductor sheets (32P is laterally offset from corresponding edges of the 14P’-2, 14P’3, 15P’-1, and 15P’-2, FIG. 13), wherein a space (lateral spaces formed on opposite sides of 32P; hereinafter ‘20P’) created by the laterally offset dielectric of the vertical cluster (20P are created by the laterally offset dielectric of CR14PS and CR15PS) is filled with the gate dielectric (20P is filled with 20 of the gate dielectric, FIG. 13).
Regarding claim 13, Lee teaches the semiconductor device of claim 10, wherein the dielectric material that is present between the pair of semiconductor sheets (DM) has a same composition as a composition of the gate dielectric (the composition of 32-3 and 32-5 of DM is the same as that of 32-2, 32-4, 32-6 of the gate dielectric, [0067]).
Regarding claim 14, Lee teaches the semiconductor device of claim 13, further including a base dielectric isolation layer (11, FIG. 13, [0040]) present between a first of the vertical clusters in the channel and a supporting substrate (10, [0025]; 11 present between CR14PS and 10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2019/0131395) in view of Lu et al. (US 2019/0131403; hereinafter ‘Lu’).
Regarding claim 8, Lee teaches the semiconductor device of claim 6, wherein a channel cluster (14PS and 15PS correspond to the channel clusters because they function as the respective channels of the pFET and nFET devices, FIG. 13, [0072-0073]; hereinafter ‘CR14PS’ and ‘CR15PS’) is provided by the at least one pair of stacked semiconductor sheets having the space between the stacked semiconductor sheets filled with the dielectric material of the gate dielectric (CR14PS is provided by 14PS having S between 14P’-2 and 14P’-3 filled with 32; and CR15PS is provided by 15PS having S between 15P’-1 and 15P’-2 filled with 32, FIG. 13).
Lee does not teach the semiconductor device wherein a portion of the gate dielectric having a conformal thickness is present on exterior surfaces of the channel cluster.
Lu teaches a semiconductor device (FIG. 38C, [0065]) wherein a portion of the gate dielectric having a conformal thickness is present on exterior surfaces of the channel cluster (the gate dielectric of gate structure 415 is conformally present on exposed exterior surfaces of channel cluster 403 because 415 has the same structure as gate structure 115, which includes gate dielectric 113 conformally formed on exposed semiconductor surfaces, FIGS. 16B and 38C, [0035, 0068])
As taught by Lu, one of ordinary skill in the art would utilize and modify the above teaching into Lee to obtain and achieve the semiconductor device wherein a portion of the gate dielectric having a conformal thickness is present on exterior surfaces of the channel cluster as claimed, because the gate electrode surrounds the channel cluster while remaining electrically insulated from its exterior semiconductor surfaces, thereby providing gate control over a greater surface area of the channel cluster [0035, 0068].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lu in combination with Lee due to the above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new grounds of rejections based on newly applied prior art. The claims were not amended in a manner that overcomes the newly applied rejections. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that More et al. (US 2021/0408230), Reznicek et al. (US 2020/0006479), Zhang et al. (US 2019/0319095), and Yang et al. (US 2022/0271032) as a semiconductor device having at least one pair of stacked semiconductor sheets for channel regions.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/10/26
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