DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2021/0193577) in view of Liu et al. (US 2021/0343673).
Regarding claim 1, Lin discloses a system, comprising:
a first die comprising a first side with first die-to-die circuitry and first input output circuitry (18, right side, figs. 1-3 and paragraphs 0014-0019);
a second die comprising a second side with second die-to-die circuitry and second input output circuitry (18, left side, figs. 1-3 and paragraphs 0014-0019), wherein the first and second sides are adjacent to each other (figs. 1-3); and
a semiconductor bridge (EN2, figs. 1H, 3, and paragraphs 0040, 0029) comprising:
a plurality of connections to interconnect the first and second die-to-die circuitries (paragraph 0029); and
a plurality of through-substrate-vias directly coupled to the first input output circuitry and the second input output circuitry (16, fig. 3 and paragraph 0019) and passing through the semiconductor bridge (EN2, figs. 1H, 3 and paragraphs 0040, 0029), the plurality of through-substrate-vias to transmit data to or from the first and second input output circuitries through the semiconductor bridge distinct from and in addition to data sent through the first and second die-to-die circuitries (30, fig. 3 and paragraphs 0047-0054). Lin discloses an encapsulated semiconductor bridge (EN2, figs. 1H, 3 and paragraphs 0040, 0029) with through-substrate-vias located in the encapsulation region and not the silicon region. However, it was well known in the art at the time of filing that silicon bridge dies may have TSVs therein and therefore it would have been obvious to one of ordinary skill in the art at the time of filing to incorporate a silicon bridge die with a TSV in the silicon region in place of a bridge die with a TSV in the encapsulation region since both function the same and both were available at the time. To illustrate such known teachings see Liu (Bridge W/TSV, fig. 1 and paragraph 0018).
Regarding claim 2, Lin further discloses an integrated circuit device package comprising the first die (18, right side, fig. 3), the second die (18, left side, fig. 3), and the semiconductor bridge (36, fig. 3).
Regarding claim 3, Lin further discloses wherein the plurality of through-silicon-vias to at least partially provide a connection from first die and the second die to electronic devices outside of the integrated circuit device package (fig. 3 and paragraph 0054).
Regarding claim 4, Lin further discloses a plurality of bumps coupled to a side of the bridge away from the first and second die, wherein the plurality of bumps are to at least partially provide the connection from the first die and the second die to the electronic devices outside of the integrated circuit device package (52, fig. 3 and paragraphs 0050-0054).
Regarding claim 5, Lin further discloses wherein the plurality of through-silicon-vias comprises: a first set of through-silicon-vias transporting first sets of data to and from the first die through the semiconductor bridge without transporting the first sets of data between first die and the second die (30, right side, fig. 3); and
a second set of through-silicon-vias transporting second sets of data to and from the second die without transporting the second sets of data between the second die and the first die (30, left side, fig. 3).
Regarding claim 6, Lin further discloses wherein the first input output circuitry is on an outermost edge on the first side (fig. 3).
Regarding claim 8, Lin further discloses wherein the second input output circuitry is on an outermost edge on the second side (fig. 3).
Regarding claim 17, Lin discloses an electronic package device, comprising:
a first die comprising a first side with first die-to-die circuitry and first input output circuitry (18, right side, figs. 1-3 and paragraphs 0014-0019);
a second die comprising a second side with second die-to-die circuitry and second input output circuitry, wherein the first and second sides are adjacent to each other in the electronic package device (18, left side, figs. 1-3 and paragraphs 0014-0019); and
an interconnect (EN2, figs. 1H, 3, and paragraphs 0040, 0029) comprising:
a plurality of connections to interconnect the first and second die-to-die circuitries (paragraph 0029); and
a plurality of through-substrate-vias directly coupled to the first input output circuitry and the second input output circuitry and passing through the interconnect, the plurality of through-substrate-vias to transmit data to or from the first and second input output circuitries through the interconnect distinct from and in addition to data sent between the first and second die-to-die circuitries (30, fig. 3 and paragraphs 0047-0054).
Lin discloses an encapsulated semiconductor bridge (EN2, figs. 1H, 3 and paragraphs 0040, 0029) with through-substrate-vias located in the encapsulation region and not the silicon region. However, it was well known in the art at the time of filing that silicon bridge dies may have TSVs therein and therefore it would have been obvious to one of ordinary skill in the art at the time of filing to incorporate a silicon bridge die with a TSV in the silicon region in place of a bridge die with a TSV in the encapsulation region since both function the same and both were available at the time. To illustrate such known teachings see Liu (Bridge W/TSV, fig. 1 and paragraph 0018).
Regarding claim 18, Lin further discloses wherein the interconnect comprises a silicon bridge, an interposer, or a combination thereof (paragraph 0032).
Regarding claim 19, Lin further discloses wherein the interconnect comprises an active interposer, an active bridge, or a combination thereof (paragraph 0032).
Regarding claims 7, 9 and 20, Lin in view of Liu discloses the system of claim 6 and the package of claim 17, as mentioned above. Lin does not explicitly disclose wherein the first die-to-die circuitry is between the first input output circuitry and a compute portion of the first die and the second die-to-die circuitry is between the second input output circuitry and a compute portion of the second die. However, Lin does disclose wherein the dies can be selected from a wide variety of types including ASIC chips (Application Specific Integrated Circuit chips) (paragraph 0014). As such, it would have been obvious to one of ordinary skill in the art at the time of filing to incorporate such chip configurations given Lin’s disclosure.
Response to Arguments
Applicant's arguments filed 5/22/26 have been fully considered but they are not persuasive. Applicant has amended the independent claims to include the limitation that “a plurality of through-silicon-vias directly coupled to the first input output circuitry and the second input output circuitry and passing through the semiconductor bridge,” and argues that Lin does not disclose such features because Lin discloses an encapsulated semiconductor bridge that has through-substrate-vias in the encapsulation region and not the semiconductor region of the bridge. Applicant is correct and the amended claim language differs from Lin’s teachings. However, as mentioned in the above rejection, semiconductor bridges with TSVs in the semiconductor region were well known at the time and would be deemed as an obvious substitution to one of ordinary skill in the art at the time of filing.
Furthermore, Applicant’s arguments with regards to claims 7, 9 and 20 are not persuasive since the broadest reasonable interpretation of “a compute portion of a semiconductor die” would merely be a couple of transistors and not a particular configuration.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 7/22/26
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