DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2021/0193577).
Regarding claim 1, Lin discloses a system, comprising:
a first die comprising a first side with first die-to-die circuitry and first input output circuitry (18, right side, figs. 1-3 and paragraphs 0014-0019);
a second die comprising a second side with second die-to-die circuitry and second input output circuitry (18, left side, figs. 1-3 and paragraphs 0014-0019), wherein the first and second sides are adjacent to each other (figs. 1-3); and
a semiconductor bridge (EN2, figs. 1H, 3, and paragraphs 0040, 0029) comprising:
a plurality of connections to interconnect the first and second die-to-die circuitries (paragraph 0029); and
a plurality of through-silicon-vias to transmit data to or from the first and second input output circuitries through the semiconductor bridge distinct from and in addition to data sent through the first and second die-to-die circuitries (30, 60, fig. 3 and paragraphs 0047-0054).
Regarding claim 2, Lin further discloses an integrated circuit device package comprising the first die (18, right side, fig. 3), the second die (18, left side, fig. 3), and the semiconductor bridge (36, fig. 3).
Regarding claim 3, Lin further discloses wherein the plurality of through-silicon-vias to at least partially provide a connection from first die and the second die to electronic devices outside of the integrated circuit device package (fig. 3 and paragraph 0054).
Regarding claim 4, Lin further discloses a plurality of bumps coupled to a side of the bridge away from the first and second die, wherein the plurality of bumps are to at least partially provide the connection from the first die and the second die to the electronic devices outside of the integrated circuit device package (52, fig. 3 and paragraphs 0050-0054).
Regarding claim 5, Lin further discloses wherein the plurality of through-silicon-vias comprises: a first set of through-silicon-vias transporting first sets of data to and from the first die through the semiconductor bridge without transporting the first sets of data between first die and the second die (30, right side, fig. 3); and
a second set of through-silicon-vias transporting second sets of data to and from the second die without transporting the second sets of data between the second die and the first die (30, left side, fig. 3).
Regarding claim 6, Lin further discloses wherein the first input output circuitry is on an outermost edge on the first side (fig. 3).
Regarding claim 8, Lin further discloses wherein the second input output circuitry is on an outermost edge on the second side (fig. 3).
Regarding claim 17, Lin discloses an electronic package device, comprising:
a first die comprising a first side with first die-to-die circuitry and first input output circuitry (18, right side, figs. 1-3 and paragraphs 0014-0019);
a second die comprising a second side with second die-to-die circuitry and second input output circuitry, wherein the first and second sides are adjacent to each other in the electronic package device (18, left side, figs. 1-3 and paragraphs 0014-0019); and
an interconnect (EN2, figs. 1H, 3, and paragraphs 0040, 0029) comprising:
a plurality of connections to interconnect the first and second die-to-die circuitries (paragraph 0029); and
a plurality of through-silicon-vias to transmit data to or from the first and second input output circuitries through the interconnect distinct from and in addition to data sent between the first and second die-to-die circuitries (30, 60, fig. 3 and paragraphs 0047-0054).
Regarding claim 18, Lin further discloses wherein the interconnect comprises a silicon bridge, an interposer, or a combination thereof (paragraph 0032).
Regarding claim 19, Lin further discloses wherein the interconnect comprises an active interposer, an active bridge, or a combination thereof (paragraph 0032).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2021/0193577).
Regarding claims 7, 9 and 20, Lin discloses the system of claim 6 and the package of claim 17, as mentioned above. Lin does not explicitly disclose wherein the first die-to-die circuitry is between the first input output circuitry and a compute portion of the first die and the second die-to-die circuitry is between the second input output circuitry and a compute portion of the second die. However, Lin does disclose wherein the dies can be selected from a wide variety of types including ASIC chips (Application Specific Integrated Circuit chips) (paragraph 0014). As such, it would have been obvious to one of ordinary skill in the art at the time of filing to incorporate such chip configurations given Lin’s disclosure.
Response to Arguments
Applicant's arguments filed 3/31/26 have been fully considered but they are not persuasive. Applicant has amended independent claim 1 to include the limitation that “a plurality of through-silicon-vias to transmit data to or from the first and second input output circuitries through the semiconductor bridge distinct from and in addition to data sent through the first and second die-to-die circuitries.” Additionally, Applicant has amended independent claim 17 to include the limitation that “a plurality of through-silicon-vias to transmit data to or from the first and second input output circuitries through the interconnect distinct from and in addition to data sent through the first and second die-to-die circuitries.” And argues that Lin does not disclose such features.
Upon further review of the Lin reference and mentioned in the above rejection, Examiner now associates the semiconductor bridge (claim 1) and the interconnect (claim 17) to the encapsulated semiconductor device (EN2, figs. 1H, 3 and paragraph 0040). As such, vias 30 anticipate the new limitation “… distinct from and in addition to data sent through the first and second die-to-die circuitries.”
Applicant has also amended claim 5 with similar language which has been rejected under the same rationale.
Examiner also notes with appreciation that Applicant has amended the withdrawn claims to include the same amended language and encourages Applicant to continue to do so to facilitate a rejoinder should allowable subject matter be found.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 4/7/26