DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on April 28, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 16-17 and 21-23 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Kim et al. (US 2020/0058567, hereinafter Kim).
Regarding claim 1, Kim discloses for a semiconductor assembly comprising that
a glass substrate (core layer 14, Figs. 3A-3I) of a glass material, because “the core layer 14 can include one or more of glass, quartz, sapphire, ER4 (flame retardant 4), ceramic, etc.” (emphasis added, [0030]), therefore, the glass core layer 14 by Kim ([0054]) corresponds to the glass substrate in the claimed invention,
the glass material (14, Figs. 3A-3I) having a first surface (top surface of 14, Figs. 3A-3I) and a second surface (bottom surface of 14, Figs. 3A-3I) opposite the first surface (top surface of 14, Figs. 3A-3I), wherein the glass substrate (14, Figs. 3A-3I) includes one or more cavities (cavity 22, Fig. 3C) in the glass material (14, Figs. 3A-3I);
a component (die 20, Figs. 3A-3I) embedded in the one or more cavities (22, Fig. 3D) of the glass substrate (14, Fig. 3D); and
a semiconductor die (device 30, Fig. 1) attached to the substrate (14, Fig. 1), because “the integrated circuit package 10 can include any suitable number of devices 30. Further, the integrated circuit package 10 can include any suitable devices, e.g., at least one of a capacitor, resistor, passive integrated capacitor system, logic circuit, analog circuit, etc.” ([0046]), therefore, the device 30 by Kim corresponds to the semiconductor die in the claimed invention,
wherein a distance between the semiconductor die and the first surface is smaller than a distance between the semiconductor die and the second surface, because the device 30 of Kim is attached above the glass core layer 14, and therefore, a distance between the device 30 and the top surface of the glass core layer 14 is less than a distance between the device 30 and the bottom surface of the glass core layer 14 (Fig. 1).
Regarding claim 2, Kim further discloses for the semiconductor assembly of claim 1 that a conductive fill (conductive via 47, Figs. 3A-3I) in the one or more cavities (cavity within the core layer 14 where the conductive via 47 is positioned, Figs. 3A-3I), the conductive fill (47, Figs. 3A-3I) electrically coupled with the component (20, Fig. 3H), because the conductive via 47 on the left and right side of the conductive via 47 in Kim (Fig. 3H) is electrically coupled with the die 20 through the second and third patterned conductive layers 34 and 46, Fig. 3H).
Regarding claim 3, Kim further discloses for the semiconductor assembly of claim 1 that the one or more cavities (cavity where the conductive vias 47 is located, Figs. 3A-3I) comprise a first conduction point (arbitrary point on the right conductive via 47, Fig. 3H) and a second conduction point (arbitrary point on the left conductive via 47, Fig. 3H), and wherein the component (20, Fig. 3H) is electrically coupled between the first conduction point and the second conduction point, because Applicants do not specifically claim where a first and a section conduction points are located, the Merriam-Webster dictionary defines a word “point” as “a very small mark”, and two arbitrary small marks on the right and left conductive vias 47 by Kim can be selected as the claimed “first conduction point” and “section conduction point”, and therefore, the die 20 is electrically coupled therebetween.
Regarding claim 5, Kim further discloses for the semiconductor assembly of claim 1 that the component (20, Figs. 3A-3I) comprises a diode, because “the one or more dies 20 can include one or more field effect transistors (FETs), metal oxide semiconductors (MOS), MOSFETs, insulated gate bipolar junction transistors (IGBT), thyristors, bipolar transistors, diodes, MOS-controlled thyristors, resistors, capacitors, etc.” (emphasis added, [0037]).
Regarding claim 16, Kim further discloses for a semiconductor substrate comprising that
a glass core (core layer 14, Figs. 3A-3I) comprising a glass material having a first surface and a second surface opposite the first surface, because “the core layer 14 can include one or more of glass, quartz, sapphire, ER4 (flame retardant 4), ceramic, etc.” (emphasis added, [0030]), therefore, the core layer 14 by Kim corresponds to the glass substrate in the claimed invention, and a top surface and bottom surface of the core layer 14 correspond do the first surface and second surface in the claimed invention, respectively,
wherein the glass core (14, Figs. 3A-3I) further includes a first conductive portion (portion of the right conductive via 47, Fig. 3H) and a second conductive portion (portion of the left conductive via 47, Fig. 3H) at least partially embedded in the glass material (14, Fig. 3H), because Applicants do not specifically claim where the first and second conductive portions are positioned, and/or what dimensions or geometrical configurations they have, the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, and therefore, a portion of the right and left conductive vias 47 within the core layer 14 can be selected as the claimed first and second conductive portions in the claimed invention, and the conductive vias 47 are fully or “at least partially” embedded in the core layer 14, each of the conductive portions (portions of right and left 47, Fig. 3H) filled with a conductive material (conductive vias, [0043]); and
a component (die 20, Figs. 3A-3I) embedded in a recess in the first surface of the glass material (cavity in the top surface of 14, Figs. 3C-3D), the component (20, Figs. 3A-3I) conductively coupled between the first conductive portion (portion of right 47, Figs. 3G-3H) and the second conductive portion (portion of left 47, Figs. 3G-3H),
wherein the first conductive portion (portion of right 47, Figs. 3G-3H) includes a through-glass via (TGV), the TGV extending from the first surface to the second surface of the glass material, because the conductive vias 47 by Kim penetrates and extends from the top surface to the bottom surface of the glass core layer 14 (Figs. 3G-3H), therefore, the conductive vias by Kim correspond to the through-glass via (TGV) in the claimed invention.
Regarding claim 17, Kim further discloses for the semiconductor substrate of claim 16 that the component (20, Figs. 3A-3H) comprises: a capacitor, a diode, a resist, a transistor, or an inductor, because “the one or more dies 20 can include one or more field effect transistors (FETs), metal oxide semiconductors (MOS), MOSFETs, insulated gate bipolar junction transistors (IGBT), thyristors, bipolar transistors, diodes, MOS-controlled thyristors, resistors, capacitors, etc” (emphasis added, [0037]).
Regarding claim 21, Kim further discloses for the semiconductor assembly of claim 1 that the one or more cavities (cavity 22, Fig. 3C) include one or more recesses in the first surface of the glass material (top surface of the core layer 14, Figs. 3A-3I).
Regarding claim 22, Kim further discloses for the semiconductor assembly of claim 3 that the first conduction point (arbitrary point on the left conductive via 47, Fig. 3H) is in the one or more cavities (cavity where the conductive vias 47 are located, Figs. 3A-3I) of the glass substrate (14, Figs. 3A-3I).
Regarding claim 23, Kim further discloses for the semiconductor assembly of claim 3 that the first conduction point (arbitrary point on the left conductive via 47, Fig. 3H) is a via (47, Fig. 3H, [0043]) comprising a conductive material (“conductive” vias, [0043]), the via (47, Fig. 3H) extending from the first surface of the glass material (top surface of the glass core layer 14, Figs. 3G-3H) to the second surface of the glass material (bottom surface of the glass core layer 14, Figs. 3G-3H).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over by Kim et al. (US 2020/0058567, hereinafter Kim) in view of Pietambaram et al. (US 2022/0375865; filed: May 18, 2021, hereinafter Pietambaram).
Regarding claim 4, Kim does not explicitly disclose that a surface of the component is flush with the first surface of the glass material.
However, Pietambaram discloses for microelectronic assemblies with glass substrates that the assembly includes a glass substrate 104-1 (Fig. 1, [0019]) having integrated magnetic core inductors (MCI) 190A and 190B (dotted box, Fig. 1), which correspond to the component in the claimed invention, and a surface of the 190A/190B lies flush with a surface of the glass substrate 104-1.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device assembly of Kim to include electronic components integrated into a glass substrate with a top surface flush with a surface of the glass substrate, as disclosed by Pietambaram, as a matter of design choice to improve overall device performance and packaging efficiency.
Regarding claim 15, Kim differs from the claimed invention by not showing that the component comprises a magnetic paste or a magnetic ink.
However, Pietambaram further discloses that the integrated magnetic core inductors (MCI) 190A/190B, which corresponds to the component in the claimed invention, includes the magnetic material 194 (Fig. 4) and “a magnetic material may include a high magnetic permeability paste or liquid suitable for filling the TGV openings” (emphasis added, [0024]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the magnetic paste in the magnetic core inductor, as disclosed by Pietambaram, in order to improve overall device performance and packaging efficiency.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2020/0058567, hereinafter Kim) in view of Ramachandran et al. (US 2016/0043068, hereinafter Ramachandran).
Regarding claim 6, Kim does not explicitly disclose that the diode comprises a P-N junction diode.
However, Ramachandran discloses for integrated interposer including a glass substrate that the interposer substrate 120 may include glass ([0044]) and diodes 150 are embedded into the interposer substrate 120 (Fig. 1), and therefore, the diodes 150 by Ramachandran corresponds to the component in the claimed invention. Ramachandran further discloses that the diode (150, Fig. 1 and 6) comprises a P-N junction diode, because the diode 150 by Ramachandran includes p-type region 156-1 and n-type region 154-1 (see Fig. 6), therefore, it comprises the P-N junction diode.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device assembly of Kim to include active electronic components, such as P-N junction diodes, integrated into a glass substrate, as disclosed by Ramachandran, in order to provide multi-functional integration and improve overall device performance and packaging efficiency, which constitutes a predictable use of prior art elements according to their established functions.
Regarding claim 14, Kim in view of Ramachandran does not explicitly disclose that the component comprises strontium, titanium, barium, or combination thereof.
However, Ramachandran further discloses that the conductive liner material 138 is disposed on the diode 150 (see Fig. 8), and therefore, the diode 150 includes the conductive liner material 138; and “the conductive liner material 138 may be nickel, titanium, cobalt or other like conductive material” (emphasis added, [0038]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit conductive materials on the diode embedded into the glass substrate, such as titanium, as disclosed by Ramachandran, in order to improve overall device performance and packaging efficiency.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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