Prosecution Insights
Last updated: April 19, 2026
Application No. 17/957,225

INTEGRATED POWER DELIVERY REGULATION CIRCUITS IN GLASS CORE USING EMBEDDED ACTIVE AND PASSIVE COMPONENTS

Non-Final OA §102§103
Filed
Sep 30, 2022
Examiner
LEE, WOO KYUNG
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
98%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
132 granted / 166 resolved
+11.5% vs TC avg
Strong +18% interview lift
Without
With
+18.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
38 currently pending
Career history
204
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
24.2%
-15.8% vs TC avg
§112
28.1%
-11.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 166 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election without traverse of Group I (device), Species A of Fig. 2, claims 1-6, 14-17, in the reply filed on December 26, 2025 is acknowledged. Examiner notes that claim 7 is not directed to the elected Species A of Fig. 2, because claim 7 is directed to the Species B of Figs. 3-4 from the previous restriction requirement; claim 11 is not directed to the elected Species A, because claim 11 is directed to the Species D of Fig. 6 from the previous restriction requirement. Therefore, claims 1-6 and 14-17 are presented for examination. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3 and 16-17 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Yun et al. (US 2018/0026666, hereinafter Yun). Regarding claim 1, Yun discloses for a semiconductor assembly comprising that a glass substrate (glass substrate 102, Fig. 2) comprising one or more cavities in a patterned portion (two cavities formed on an upper side of the glass substrate 102, Fig. 2); a component (MIM capacitor 216, Fig. 2) embedded into the glass substrate (102, Fig. 2) at the patterned portion (a portion below the contact 224, Fig. 2), the component (216, Fig. 2) at least partially embedded in the glass core, because the MIM capacitor 216 by Yun is fully embedded into the glass substrate 102, which includes the claimed limitation “at least partially embedded”; and a semiconductor die (semiconductor die 106, Fig. 2) attached to the substrate (102, Fig. 2), because Applicants do not specifically claim where a semiconductor die is positioned and/or where it is attached to the substrate, for example, whether it is attached to a upper surface of the substrate or to a lower surface of the substrate, the semiconductor die 106 by Yun is attached to an inside of the glass substrate 102 (Fig. 2). Regarding claim 2, Yun further discloses for the semiconductor assembly of claim 1 that a conductive fill (contact 224, Fig. 2) in the one or more cavities (cavity where the contact 224 is located, Fig. 2), the conductive fill (224, Fig. 2) electrically connected to the component (216, Fig. 2). Regarding claim 3, Yun further discloses for the semiconductor assembly of claim 1 that the one or more cavities (cavity where the contact 224 is located, Fig. 2) comprise a first conduction point (arbitrary point on a left edge of 224, Fig. 2) and a section conduction point (arbitrary point of a right edge of 224, Fig. 2), the component (216, Fig. 2) connected therebetween, because Applicants do not specifically claim where a first and a section conduction points are located, the Merriam-Webster dictionary defines a word “point” as “a very small mark”, and as shown in the attached Fig. 2 of Yun below, two small marks on the left and right edges of the contact 224 can be selected as the claimed “first conduction point” and “section conduction point”, and therefore, the capacitor 216 is connected therebetween. PNG media_image1.png 703 1431 media_image1.png Greyscale Regarding claim 16, Yun further discloses for a semiconductor substrate comprising that a glass core (glass substrate 102, Fig. 2) having a first patterned portion (left edge portion of the contact 224, Fig. 2) and a second patterned portion (right edge portion of the contact 224, Fig. 2), because Applicants do not specifically claim where the first and second patterned portions are positioned, and/or what dimensions or geometrical configurations they have, the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, and therefore, a left edge portion of the cavity where the contact 224 is formed can correspond to the claimed first patterned portion and a right edge portion of the cavity where the contact 242 is formed can correspond to the claimed second patterned portion, each of the patterned portions (left edge and right edge of 224, Fig. 2) filled with a conductive material (224, Fig. 2); a component (capacitor 216, Fig. 2) embedded in the glass core (102, Fig. 2), the component (216, Fig. 2) extending between the first patterned portion (left edge of 224, Fig. 2) and the second patterned portion (right edge of 224, Fig. 2), wherein the component (216, Fig. 2) is electrically connected through the conductive material (224, Fig. 2). Regarding claim 17, Yun further discloses for the semiconductor substrate of claim 16 that the component comprises: a capacitor (capacitor 216, Fig. 2), a diode, a resist, a transistor, or an inductor. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over by Yun et al. (US 2018/0026666, hereinafter Yun) in view of Pietambaram et al. (US 2022/0375865; filed: May 18, 2021, hereinafter Pietambaram) The teachings of Yun et al. are discussed above. Regarding claim 4, Yun discloses for the semiconductor assembly of claim 1 that the component (capacitor 216, Fig. 2) is at least partially embedded in the glass core (glass substrate 102, Fig. 2), because the capacitor 216 by Yun is fully embedded in the glass substrate 102, which includes the claimed limitation “at least partially embedded”. Yun differs from the claimed invention by not showing that a surface of the component lies flush with a surface of the glass substrate. However, Pietambaram discloses for microelectronic assemblies with glass substrates that the assembly includes a glass substrate 104-1 (Fig. 1, [0019]) having integrated magnetic core inductors (MCI) 190A and 190B (dotted box, Fig. 1), which correspond to the component in the claimed invention, and a surface of the 190A/190B lies flush with a surface of the glass substrate 104-1. Since both Yun and Pietambaram teach a semiconductor device assembly with a glass substrate, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device assembly of Yun to include electronic components integrated into a glass substrate with a top surface flush with a surface of the glass substrate, as disclosed by Pietambaram, as a matter of design choice to improve overall device performance and packaging efficiency by planarizing component layers. Regarding claim 15, Yun differs from the claimed invention by not showing that the component comprises a magnetic paste or a magnetic ink. However, Pietambaram further discloses that the integrated magnetic core inductors (MCI) 190A/190B, which corresponds to the component in the claimed invention, includes the magnetic material 194 (Fig. 4) and “a magnetic material may include a high magnetic permeability paste or liquid suitable for filling the TGV openings” (emphasis added, [0024]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the magnetic paste in the magnetic core inductor, as disclosed by Pietambaram, in order to improve overall device performance and packaging efficiency by planarizing component layers. Claims 5-6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US 2018/0026666, hereinafter Yun) in view of Ramachandran et al. (US 2016/0043068, hereinafter Ramachandran) The teachings of Yun et al. are discussed above. Regarding claim 5, Yun differs from the claimed invention by not showing that the component comprises a diode. However, Ramachandran discloses for integrated interposer including a glass substrate that the interposer substrate 120 may include glass ([0044]) and diodes 150 are embedded into the interposer substrate 120 (Fig. 1), and therefore, the diodes 150 by Ramachandran corresponds to the component in the claimed invention, and one of ordinary skill in the art would acknowledge that the active components such as diodes can be integrated into the glass substrate in semiconductor device assemblies. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device assembly of Yun to include active electronic components, such as diodes, integrated into a glass substrate, as disclosed by Ramachandran, in order to provide multi-functional integration and improve overall device performance and packaging efficiency, which constitutes a predictable use of prior art elements according to their established functions. Regarding claim 6, Ramachandran further discloses that the diode (150, Fig. 1 and 6) comprises a P-N junction diode, because the diode 150 by Ramachandran includes p-type region 156-1 and n-type region 154-1 (see Fig. 6), therefore, it comprises the P-N junction diode. Regarding claim 14, Yun in view of Ramachandran does not explicitly disclose that the component comprises strontium, titanium, barium, or combination thereof. However, Ramachandran further discloses that the conductive liner material 138 is disposed on the diode 150 (see Fig. 8), and therefore, the diode 150 includes the conductive liner material 138; and “the conductive liner material 138 may be nickel, titanium, cobalt or other like conductive material” (emphasis added, [0038]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit conductive materials on the diode embedded into the glass substrate, such as titanium, as disclosed by Ramachandran, in order to improve overall device performance and packaging efficiency. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WOO K LEE/Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Sep 30, 2022
Application Filed
Oct 18, 2022
Response after Non-Final Action
May 11, 2023
Response after Non-Final Action
Feb 11, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
98%
With Interview (+18.4%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 166 resolved cases by this examiner. Grant probability derived from career allow rate.

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