DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of claim(s) 7 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 7 has been withdrawn.
RE: the rejection of the claims under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 11, 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 includes “the conductive pad lies flush with a surface of the glass substrate” and it is unclear if this was intended to refer to one or both of the first and second conductive pads in claim 1. For the purposes of examination, this will be interpreted as “the first conductive pad or the second conductive pad lies flush with a surface of the glass substrate.”
Claim 11 includes “wherein the dielectric layer isolates the metallic pad” and since claim 9 includes “each of the metallic pads comprises copper” and since claim 8 includes “each of the conductive pads comprises a metallic pad,” it is unclear if the metallic pad in claim 11 was intended to refer to each of the metallic pads or just one of them. For the purposes of examination the above limitation will be interpreted as “wherein the dielectric layer isolates one of the metallic pads.”
Claim 21 includes “the first conductive pad is in contact with … a portion of the glass substrate” and “the second conductive pad is in contact with … a portion of the glass substrate” and it is unclear if these are the same or different portions. For the purposes of examination these will be interpreted as different portions.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20050244999A1 (“Masuyama”) in view of US 20190348265 A1 (“Steiner”), further in view of KR20100122678A (“Kang”), further in view of US20020130358A1
(“Van Dalen”), further in view of US20180338379A1 (“Bemmerl”).
RE: Claim 1, Masuyama discloses A semiconductor package (package in FIG. 10), comprising:
a substrate (24) comprising:
a via (opening in 24 for 56) extending through the substrate;
a coating (56, [0042]) in contact with an internal surface of the via (FIG. 10 shows coating 56 in direct contact with an internal surface of the via/opening in 24 for 56);
a first conductive pad (combination of 12 and 58; 12 is a copper pad [0042], 58 is a conductive cap, [0044]) on the first end (top end) of the via, the first conductive pad extending over the coating and a portion of the substrate (FIG. 10 shows 12, 58 extending over the coating 56 and a portion of the substrate 24); and
a second conductive pad (combination of 14 and 60; 14 is a copper pad [0042], 60 is a conductive cap, [0044]) on the second end (bottom end) of the via,
the second conductive pad extending over the coating and a portion of the substrate (FIG. 10 shows the second conductive pad 14, 60 extending over the coating 56 and a portion of the substrate 24).
Masuyama does not explicitly disclose:
the substrate is a glass substrate;
the substrate comprises an embedded varistor, the varistor comprising the via;
the coating comprising cobalt, zinc, and oxygen;
a plug material within the via and in contact with an internal surface of the coating, wherein:
the plug material is an insulating dielectric;
the plug material is coplanar with the coating and coplanar with a first side of the glass substrate at a first end of the via; and
the plug material is coplanar with the coating and coplanar with a second, opposite, side of the glass substrate at a second, opposite, end of the via;
the first conductive pad extends over the plug material;
the second conductive pad extends over the plug material;
a semiconductor die attached to the substrate;
the semiconductor die coupled to a voltage regulation circuit including the varistor.
However, Masuyama discloses the substrate 24 is a printed circuit board.
In the same field of endeavor, Steiner discloses Preferably, the printed circuit boards are made of plastic, glass or ceramic material, [0022]. Accordingly, there was a need to select a material for the printed circuit board 24 in Masuyama before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the printed circuit board 24 out of glass as this would have been obvious to try since glass is one solution for the material in a printed circuit board identified by Steiner and this would have had a reasonable expectation of success, see MPEP 2143.
In the same field of endeavor, Kang discloses The protective via 40 is formed by filling a varistor paste in a via hole formed in the body 10, pg. 5, lines 10-12; see FIG. 3.
Kang further discloses The varistor paste includes, for example, at least one of ZnO, Bi2O3, CoO, pg. 5, lines 14-15. Accordingly, Kang discloses varistor paste including ZnO, Bi2O3, and CoO.
Kang further discloses The varistor paste has the same characteristics as a varistor, pg. 5, lines 22-24.
Kang further discloses since the resistances of the first and second protective vias 40a and 40b are large, the first and second protective vias 40a and 40b are electrically open, pg. 6, lines 7-8.
Kang further discloses when a high voltage occurs due to a sudden electrostatic discharge, the resistance of the first protective via 40a and / or the second protective via 40b is drastically reduced, so that the first protective via 40a or / and the first The two protective vias 40b are electrically close to a short. Accordingly, no current flows through the light emitting diode 20, and a current flows to the ground through the first protective via 40a at a positive voltage or through the second protective via 40b at ground, pg. 6, lines 11-16.
Accordingly, the protection via 40a, 40b, which is coupled to the light emitting diode/semiconductor die 20, prevents current flowing through the light emitting diode/semiconductor die 20 when a high voltage occurs, and would therefore regulate or control a voltage of the light emitting diode/semiconductor die 20. Accordingly, the protection via 40a, 40b would be part of a voltage regulation circuit.
Kang further discloses the protective via 40 connects a first electrode 31 to ground 50, pg. 5, lines 1-3.
Kang further discloses The protective vias 240 may protect the light emitting diodes 220 from excessive currents generated by electrostatic discharge (ESD) or surge, pg. 5 lines 7-8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the resistive coating 56 to include varistor resistive material including zinc oxide (ZnO) with cobalt oxide (CoO) and bismuth oxide (Bi2O3), and to use the resistive coating 56 as a protection via included in a voltage regulation circuit coupled to the electronic component 26 as taught by Kang in order to protect the electronic component 26 from high voltage surges and/or excess current as further taught by Kang. As a result, the internal surface of the opening in 24 would be coated in a material comprising cobalt, zinc, and oxygen.
In the same field of endeavor, Van Dalen discloses in FIG. 8:
a plug material (46) within a via (opening for 42a, 48, defined by 44) and in contact with an internal surface of a coating (FIG. 8 shows 46 is in contact with an internal surface of coating 42a, 48; 42a is part of a resistive path, [0055]; 48 is part of the resistive path, [0058]; Accordingly, the combination of 42a, 48 correspond to a resistive coating), wherein:
the plug material is an insulating dielectric (insulating filler material 46 may be a deposited silicon dioxide, [0055]; the instant application identifies the plug material as an insulating dielectric material such as silicon dioxide, [0061]; Accordingly, silicon dioxide is an insulating dielectric);
the plug material is coplanar with the coating and coplanar with a first side of a substrate (first top side of the combination of 24, 20) at a first end of the via (FIG. 8 shows the plug material 46 is coplanar with the coating 48 and coplanar with a first top side of a substrate 20, 24 at a first top end of the via/opening for 42a, 48); and
the plug material is coplanar with the coating and coplanar with a second, opposite, side of the substrate at a second, opposite, end of the via (FIG. 8 shows the plug material 46 is coplanar with the coating 42a and coplanar with a second, opposite, bottom side of the substrate 24, 20 at a second, opposite, end of the via/opening for 42a, 48);
a first conductive pad (31, [0023]) extends over the plug material;
a second conductive pad (22 or 32; 22 is highly doped such that its potential corresponds to electrode 32, [0034]; Accordingly, 22 is conductive) extends over the plug material.
In FIG. 8, Van Dalen discloses that the plug material 46 is coplanar with a top surface of the resistive coating 46, 48, and coplanar with a bottom surface of the resistive coating 46, 48.
Van Dalen further discloses:
the width of the trench 41 provides the cross-section that determines the resistance of the path 42. Extra degrees of freedom in determining this resistance value and in determining the different levels 81 and 82 can be achieved using an additional insulating in-fill 46, for example as illustrated in FIGS. 7 and 8, [0054].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an insulating plug material in contact with an internal surface of the resistive coating 56 such that the insulating plug material is coplanar with a top surface of the resistive coating 56, and coplanar with a bottom surface of the resistive coating 56 as taught by Van Dalen in order to better control its resistance values and/or provide extra degrees of freedom in determining resistance values for the resistive coating 56 as further taught by Van Dalen. As a result, the plug material would be coplanar with a top side of the glass substrate 24, and coplanar with a bottom side of the glass substrate 24, the first conductive pad 58, 12 would extend over the plug material, and the second conductive pad 60, 14 would extend over the plug material. Further, as the modified resistive coating 56 includes varistor material, the combination of the resistive coating 56, the opening in the substrate 24 for the resistive coating 56, and the insulating plug material would correspond to the claimed varistor which would be embedded in the glass substrate 24.
In the same field of endeavor, Bemmerl discloses an electronic component 16 attached to a substrate 12, see FIG. 8, [0046], [0048].
Bemmerl discloses the electronic component 16 may be or may include at least one of a semiconductor die, a passive electronic component, a sensor, an LED, an active electronic component, a semiconductor package, [0048].
Accordingly, there was a need to select the type of electronic component 26 in Masuyama before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a semiconductor die as the electronic component 26 as this would have been obvious to try since a semiconductor die is one solution for an electronic component identified by Bemmerl and this would have had a reasonable expectation of success, see MPEP 2143. As a result, the varistor would be used as a protection via included in a voltage regulation circuit coupled to the semiconductor die 26.
RE: Claim 2, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl discloses The semiconductor package of claim 1, wherein the plug material occupies an entirety of the interior volume of the via that is not occupied by the coating (Van Dalen FIG. 8 shows the plug material 46 occupying an entirety of the interior volume of the via/opening for resistive coating 42a, 48 that is not occupied by the coating 42a, 48; Accordingly, as modified, the plug material occupies an entirety of the interior volume of the via/opening for resistive coating 56 that is not occupied by the resistive coating 56).
RE: Claim 4, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl discloses The semiconductor package of claim 2, wherein the insulating dielectric comprises silicon and oxygen (Van Dalen discloses insulating filler material 46 may be a deposited silicon dioxide, [0055]; Accordingly, as modified the insulating dielectric of the plug material comprises silicon and oxygen).
RE: Claim 5, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl discloses The semiconductor package of claim 1, wherein the conductive pad lies flush with a surface of the glass substrate (In Masuyama FIG. 10, the combination 12, 58 directly abuts and is immediately adjacent to the top surface of 24; the adjective “flush” is defined as “directly abutting or immediately adjacent,” see definition 4b by Merriam-Webster; Accordingly, the combination 12, 58 lies flush with the top surface of 24).
RE: Claim 6, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl discloses The semiconductor package of claim 1, wherein the coating has a resistance that varies with applied voltage between first and second conductive pads (Kang discloses The varistor paste has the same characteristics as a varistor. In other words, the current has a high resistance and does not flow the current, but when the excessive current is generated by the high voltage, the resistance is reduced to have a non-linear current-voltage characteristic to flow the current, pg. 5, lines 21-24; when a high voltage occurs due to a sudden electrostatic discharge, the resistance of the first protective via 40a and / or the second protective via 40b is drastically reduced, so that the first protective via 40a or / and the first The two protective vias 40b are electrically close to a short. Accordingly, no current flows through the light emitting diode 20, and a current flows to the ground, pg. 6, lines 11-16; Accordingly, in Kang, the varistor paste in 40a has a resistance that varies with applied voltage between electrode 31 and ground 50; the instant application discloses Varistors can generally have electrical resistance that varies with the applied voltage, [0047]; Accordingly, as modified, the resistive coating 56 includes varistor material and would therefore have a resistance that varies with applied voltage between the first conductive pad 12, 58 and the second conductive pad 14, 60).
RE: Claim 7, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl discloses The semiconductor package of claim 6, wherein the coating has a thickness, and the thickness is in direct contact with both of the conductive pads (In Masuyama FIG. 10, the coating 56 has a vertical thickness that is in direct contact with the first conductive pad 12, 58 and with the second conductive pad 14, 60; As modified, the vertical thickness of 56 is unchanged and therefore the coating 56 would still have a vertical thickness that is in direct contact with the first conductive pad 12, 58 and the second conductive pad 14, 60).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuyama in view Steiner, Kang, Van Dalen, Bemmerl as applied to claim 1, further in view of US20020043395 A1 (“Parker”).
RE: Claim 8, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl does not explicitly disclose The semiconductor package of claim 1, wherein each of the conductive pads comprises a metallic pad that spans a diameter of the via.
However, Masuyama discloses 12, 14 are made of copper, [0028].
In the same field of endeavor, Parker discloses the via 10 is sealed by the conductive layers 20 and 22, with the conductive layers 20 and 22 acting as a conductive cap, [0037], see FIGs. 1A-1E.
Parker further discloses layers 20, 22 are made of copper, [0037].
In FIG. 1E, each of the metal conductive layers/pads 20, 22 spanning a diameter of the via 10 or via 11.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the conductive caps 58, 60 out of copper as taught by Parker in order to seal the material of the via/opening for 56 as further taught by Parker. As a result, the first conductive pad 12, 58 and the second conductive pad 14, 60 would each be made of copper and would each span a diameter of the via/opening for 56.
RE: Claim 9, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl, Parker discloses The semiconductor package of claim 8, wherein each of the metallic pads comprises copper (As modified by Parker, the first conductive pad 12, 58 and the second conductive pad 14, 60 would each be made of copper).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuyama in view Steiner, Kang, Van Dalen, Bemmerl, Parker as applied to claim 9, further in view of US20210098423 A1 (“Chen”).
RE: Claim 10, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl, Parker does not explicitly disclose The semiconductor package of claim 9, further comprising a dielectric layer on a surface of the glass substrate.
In the same field of endeavor, Chen discloses a dielectric layer (108b, [0021], FIG. 1A) on a surface of a glass substrate (108 includes silicate glass, [0020]).
In FIG. 1A, the dielectric layer 108b is shown isolating the pads 110b in direct contact with vias 110a.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a dielectric layer on the substrate 24 as taught by Chen in order to provide isolation to the first conductive pad 12, 58 and prevent short circuiting.
RE: Claim 11, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl, Parker, Chen discloses The semiconductor package of claim 10, wherein the dielectric layer isolates the metallic pad (As modified by Chen, the dielectric layer isolates the metallic first conductive pad 12, 58).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuyama in view Steiner, Kang, Van Dalen, Bemmerl as applied to claim 1, in view of US20170179351A1 (“Palaniswamy”).
RE: Claim 21, Masuyama in view Steiner, Kang, Van Dalen, Bemmerl discloses The semiconductor package of claim 1, wherein the first conductive pad is in contact with the coating, and a portion of the glass substrate (As modified, first conductive pad 12, 58 is in direct contact with the coating 56 and the top portion of the glass substrate 24 as seen in Masuyama FIG. 10), and wherein the second conductive pad is in contact with the coating, and a portion of the glass substrate (As modified, second conductive pad 14, 60 is in direct contact with the coating 56 and the bottom portion of the glass substrate 24 as seen in Masuyama FIG. 10).
Masuyama in view Steiner, Kang, Van Dalen, Bemmerl does not explicitly disclose:
the first conductive pad is in contact with the plug material;
the second conductive pad is in contact with the plug material.
In a similar field of endeavor, Palaniswamy discloses when an element, component or layer for example is described as forming a “coincident interface” with, or being “on” “connected to,” “coupled with,” “stacked on” or “in contact with” another element, component or layer, it can be directly on, directly connected to, directly coupled with, directly stacked on, in direct contact with, or intervening elements, components or layers may be on, connected, coupled or in contact with the particular element, component or layer, for example. When an element, component or layer for example is referred to as being “directly on,” “directly connected to,” “directly coupled with,” or “directly in contact with” another element, there are no intervening elements, components or layers for example, [0019].
Accordingly, under a broad reasonable interpretation, first conductive pad 12, 58 is at least in indirect contact with the plug material through intervening coating 56, and second conductive pad 14, 60 is at least in indirect contact with the plug material through intervening coating 56.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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