DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Invention I and Species H in the reply filed on January 14 2026 is acknowledged. As the election was made without traverse, the requirement is deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 includes “wherein the material is a thin film having a thickness and the thickness is in direct contact with the conductive pad” and the terminology “thin film” is indefinite as “thin” is a subjective term and the instant specification does not supply an objective standard for measuring the scope of the term. For the purposes of examination, the terminology “thin film” will be interpreted as “film” or “film that is thin relative to another element.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5-7, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20050244999A1 (“Masuyama”) in view of US 20190348265 A1 (“Steiner”), further in view of KR20100122678A (“Kang”), further in view of US 20180338379 A1 (“Bemmerl”).
RE: Claim 1, Masuyama discloses A semiconductor assembly (assembly in FIG. 10) comprising:
a substrate (24) comprising:
a via (56 or opening in 24 for 56) extending through the substrate,
wherein an internal surface of the via is coated in a material (FIG. 10 shows the internal surface of the opening in 24 is coated in resistive material of 56; 56 is formed of resistive pastes, fills, and/or inks, [0042]);
a conductive pad (12 and 58 or 14 and 60; 12, 14 are copper pads, [0042]; 58, 60 are conductive caps, [0044]) on an end of the via.
Masuyama does not explicitly disclose the substrate is a glass substrate;
wherein the internal surface of the via is coated in a material comprising cobalt, zinc, and oxygen;
a semiconductor die attached to the glass substrate.
However, Masuyama discloses the substrate 24 is a printed circuit board.
Accordingly, there was a need to select a material for the printed circuit board 24 in Masuyama before the effective filing date of the claimed invention.
In the same field of endeavor, Steiner discloses Preferably, the printed circuit boards are made of plastic, glass or ceramic material, [0022].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the printed circuit board 24 out of glass as this would have been obvious to try since glass is one solution for the material in a printed circuit board identified by Steiner and this would have had a reasonable expectation of success, see MPEP 2143.
Further, Masuyama further discloses the printed circuit board preferably includes a plurality of through-hole vias disposed therein with a selected subset of the through-hole vias configured as resistive vias having at least one type of resistive fill disposed therein, [0003]; resistance values that may be achieved in a resistive via are substantially unlimited, [0006].
In the same field of endeavor, Kang discloses The protective via 40 is formed by filling a varistor paste in a via hole formed in the body 10, pg. 5, lines 10-12; see FIG. 3.
Kang further discloses The varistor paste includes, for example, at least one of ZnO, Bi2O3, CoO, pg. 5, lines 14-15. Accordingly, Kang discloses varistor paste including ZnO, Bi2O3, and CoO.
Kang further discloses The varistor paste has the same characteristics as a varistor, pg. 5, lines 22-24.
Kang further discloses since the resistances of the first and second protective vias 40a and 40b are large, the first and second protective vias 40a and 40b are electrically open, pg. 6, lines 7-8.
Kang further discloses when a high voltage occurs due to a sudden electrostatic discharge, the resistance of the first protective via 40a and / or the second protective via 40b is drastically reduced, pg. 6, lines 11-12.
Kang further discloses the protective via 40 connects a first electrode 31 to ground 50, pg. 5, lines 1-3.
Kang further discloses The protective vias 240 may protect the light emitting diodes 220 from excessive currents generated by electrostatic discharge (ESD) or surge, pg. 5 lines 7-8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the resistive material 56 to be made of varistor resistive material including zinc oxide (ZnO) with cobalt oxide (CoO) and bismuth oxide (Bi2O3) as taught by Kang in order to better control its resistance and to protect the electronic component 26 from surges as further taught by Kang. As a result, the internal surface of the opening in 24 would be coated in a material comprising cobalt, zinc, and oxygen.
Further, Masuyama discloses an electronic component 26 is attached to the substrate 24.
In the same field of endeavor, Bemmerl discloses an electronic component 16 attached to a substrate 12, see FIG. 8.
Bemmerl discloses the electronic component 16 may be or may include at least one of a semiconductor die, a passive electronic component, a sensor, an LED, an active electronic component, a semiconductor package, [0048].
Accordingly, there was a need to select the type of electronic component 26 in Masuyama before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a semiconductor die as the electronic component 26 as this would have been obvious to try since a semiconductor die is one solution for an electronic component identified by Bemmerl and this would have had a reasonable expectation of success, see MPEP 2143.
RE: Claim 2, Masuyama in view of Steiner, Kang, Bemmerl discloses The semiconductor assembly of claim 1, further comprising a plug material in the via (As discussed above, Kang discloses the varistor paste includes Bi2O3, pg. 5, lines 14-15, which is bismuth oxide; As modified, the plug material bismuth oxide is in the via 56 of 24,).
RE: Claim 5, Masuyama in view of Steiner, Kang, Bemmerl discloses The semiconductor assembly of claim 1, wherein the conductive pad lies flush with a surface of the glass substrate (In Masuyama FIG. 10, 12, 14 each directly abut and are immediately adjacent to surfaces of 24; the adjective “flush” is defined as “directly abutting or immediately adjacent,” see definition 4b by Merriam-Webster; Accordingly, 12, 14 lie flush with the surfaces of 24).
RE: Claim 6, Masuyama in view of Steiner, Kang, Bemmerl discloses The semiconductor assembly of claim 1, wherein the material has a resistance that varies with applied voltage (As modified, Kang discloses when a high voltage occurs due to a sudden electrostatic discharge, the resistance of the first protective via 40a and / or the second protective via 40b is drastically reduced, pg. 6, lines 11-12).
RE: Claim 7, Masuyama in view of Steiner, Kang, Bemmerl discloses The semiconductor assembly of claim 6, wherein the material is a thin film having a thickness and the thickness is in direct contact with the conductive pad (Masuyama FIG. 10 shows 56 is thin compared to the width of 12 or 24, and it has a vertical thickness in direct contact with each of 58, 60).
RE: Claim 12, Masuyama in view of Steiner, Kang, Bemmerl discloses The semiconductor assembly of claim 1, wherein the material forms a vertical varistor (As modified, the material of resistive column 56 forms a vertical varistor in 24).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuyama in view of Steiner, Kang, Bemmerl as applied to claim 2, further in view of US20140268616A1 (“Lan”).
RE: Claim 3, Masuyama in view of Steiner, Kang, Bemmerl does not explicitly disclose The semiconductor assembly of claim 2, wherein the plug material in the via comprises an insulating dielectric.
However, in the same field of endeavor, Lan discloses a via 104 with a polymer core 302, [0037], see FIG. 3.
Lan further discloses The polymer core may include at least one of polyimide (PI), benzocyclobutene (BCB), acrylic, polybenzoxazole (PBO). Having a polymer core 302 may enable the first via 104 to provide structural support, [0037].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the via 56 to have a polymer core made of polyimide as taught by Lan in order to provide improved structural support to the electronic component 26.
Further, the reference US 20040227581 A1 (“Noujeim”) identifies polyimide as a dielectric material, [0007]. Accordingly, the plug material in the via 56 would include polyimide as the claimed insulating dielectric.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuyama in view of Steiner, Kang, Bemmerl as applied to claim 2, further in view of Lan, further in view of US 20170338214 A1 (“Uzoh”).
RE: Claim 4, Masuyama in view of Steiner, Kang, Bemmerl does not explicitly disclose The semiconductor assembly of claim 2, wherein the plug material comprises a silicon and oxygen.
However, in the same field of endeavor, Lan discloses a via 104 with a polymer core 302, [0037], see FIG. 3;
Lan further discloses The polymer core may include at least one of polyimide (PI), benzocyclobutene (BCB), acrylic, polybenzoxazole (PBO). Having a polymer core 302 may enable the first via 104 to provide structural support, [0037].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the via 56 to have a polymer core made of polyimide as taught by Lan in order to provide improved structural support to the electronic component 26.
In the same field of endeavor, Uzoh discloses The second layer 15 can comprise a filler material (e.g., a polymer) filled with filler particles. For example, the second layer can comprise a composite material having a polymeric base layer filled with particles having a diameter in a range of 2 nm to 30 nm. In some embodiments, the filler particles can comprise silicon oxide or silicon nitride particles. The filler particles can enhance the hardness of the second layer 15 and can improve thermal matching with the first layer 12 and the dies 3 a, 3 b, [0050].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the polymer core in 56 to include silicon oxide filler particles as taught by Uzoh in order to enhance the hardness of the polymer core, thereby improving the structural support provided to the electronic component 24.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuyama in view of Steiner, Kang, Bemmerl as applied to claim 1, further in view of US 20020043395 A1 (“Parker”).
RE: Claim 8, Masuyama in view of Steiner, Kang, Bemmerl does not explicitly disclose The semiconductor assembly of claim 1, wherein the conductive pad comprises a metallic pad that spans a diameter of the via.
However, Masuyama discloses 12, 14 are made of copper, [0028].
In the same field of endeavor, Parker discloses the via 10 is sealed by the conductive layers 20 and 22, with the conductive layers 20 and 22 acting as a conductive cap, [0037], see FIG. 1E.
Parker further discloses layers 20, 22 are made of copper, [0037].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the conductive caps 58, 60 out of copper as taught by Parker in order to seal the material of the via 56 as further taught by Parker. As a result, 12 and 58 or 14 and 60 would correspond to the claimed metallic pad spanning the diameter of the via 56.
RE: Claim 9, Masuyama in view of Steiner, Kang, Bemmerl, Parker discloses The semiconductor assembly of claim 8, wherein the metallic pad comprises copper (As modified, 12, 14, 56, 58 are made of copper).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuyama in view of Steiner, Kang, Bemmerl, Parker as applied to claim 9, further in view of US 20210098423 A1 (“Chen”).
RE: Claim 10, Masuyama in view of Steiner, Kang, Bemmerl, Parker does not explicitly disclose The semiconductor assembly of claim 9, further comprising a dielectric layer on a surface of the glass substrate.
In the same field of endeavor, Chen discloses a dielectric layer (108b, [0021], FIG. 1A) on a surface of a glass substrate (108 includes silicate glass, [0020]).
In FIG. 1A, the dielectric layer 108b is shown isolating the pads 110b in direct contact with vias 110a.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a dielectric layer on the substrate 24 as taught by Chen in order to provide isolation to the pad 12/58 and prevent short circuiting.
RE: Claim 11, Masuyama in view of Steiner, Kang, Bemmerl, Parker, Chen discloses The semiconductor assembly of claim 10, wherein the dielectric layer isolates the metallic pad (As modified, the dielectric layer isolates the metallic pad 12/58).
Claim(s) 13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuyama in view of Steiner, further in view of Kang.
RE: Claim 13, Masuyama discloses A semiconductor substrate comprising:
a core substrate (24) comprising:
at least one via extending through the core substrate, the at least one via comprising a material having a resistance extending along the through glass via, and
end pads at each terminating end of the via.
Masuyama does not explicitly disclose the substrate is a glass core substrate;
the at least one via is an at least one through glass via;
the at least one via contains a vertical varistor comprising the material having a resistance variable with applied voltage extending along the through glass via;
circuitry coupled to the glass core substrate to operate the material as a varistor.
However, Masuyama discloses the substrate 24 is a printed circuit board.
Accordingly, there was a need to select a material for the printed circuit board 24 in Masuyama before the effective filing date of the claimed invention.
In the same field of endeavor, Steiner discloses Preferably, the printed circuit boards are made of plastic, glass or ceramic material, [0022].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the printed circuit board 24 out of glass as this would have been obvious to try since glass is one solution for the material in a printed circuit board identified by Steiner and this would have had a reasonable expectation of success, see MPEP 2143. As a result, the substrate 24 would correspond to the claimed glass core substrate, and the via 56 / opening in 24 for 56 would correspond to the claimed at least one through glass via.
Further, Masuyama further discloses the printed circuit board preferably includes a plurality of through-hole vias disposed therein with a selected subset of the through-hole vias configured as resistive vias having at least one type of resistive fill disposed therein, [0003]; resistance values that may be achieved in a resistive via are substantially unlimited, [0006].
In the same field of endeavor, Kang discloses The protective via 40 is formed by filling a varistor paste in a via hole formed in the body 10, pg. 5, lines 10-12; see FIG. 3.
Kang further discloses The varistor paste includes, for example, at least one of ZnO, Bi2O3, CoO, pg. 5, lines 14-15. Accordingly, Kang discloses varistor paste including ZnO, Bi2O3, and CoO.
Kang further discloses The varistor paste has the same characteristics as a varistor, pg. 5, lines 22-24.
Kang further discloses since the resistances of the first and second protective vias 40a and 40b are large, the first and second protective vias 40a and 40b are electrically open, pg. 6, lines 7-8.
Kang further discloses when a high voltage occurs due to a sudden electrostatic discharge, the resistance of the first protective via 40a and / or the second protective via 40b is drastically reduced, pg. 6, lines 11-12.
Kang further discloses the protective via 40 connects a first electrode 31 to ground 50, pg. 5, lines 1-3.
Kang further discloses The protective vias 240 may protect the light emitting diodes 220 from excessive currents generated by electrostatic discharge (ESD) or surge, pg. 5 lines 7-8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the resistive material 56 to be made of varistor resistive material as taught by Kang and to connect the bottom end of the varistor material to ground in order to better control its resistance and to protect the electronic component 26 from surges as further taught by Kang. As a result, the varistor material of 56 would correspond to the claimed material having a resistance variable with applied voltage.
Further, Masuyama discloses a solder ball 32 is in contact with one or more signal or power leads or contacts of electronic component 26, [0035].
Accordingly, the combination of the solder ball 32 and the electronic component 26 would correspond to the claimed circuitry as its signal or power leads would be electrically connected to the varistor material in 56 and therefore operate it as a varistor, to protect against surges.
RE: Claim 15, Masuyama in view of Steiner, Kang discloses The semiconductor substrate of claim 13, wherein the vertical varistor is embedded in the glass core substrate with a thickness of the material in direct contact with the end pads (Masuyama FIG. 10 shows 56 has a vertical thickness in direct contact with each of 58, 60).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuyama in view of Steiner, further in view of Kang as applied to claim 13, further in view of Lan.
RE: Claim 14, Masuyama in view of Steiner, Kang does not explicitly disclose The semiconductor substrate of claim 13,
wherein the through glass via further contains a plug material at least partially surrounded by the material having a resistance variable with applied voltage.
However, in the same field of endeavor, Lan discloses a via 104 with a polymer core 302, [0037], see FIG. 3.
Lan further discloses The polymer core may include at least one of polyimide (PI), benzocyclobutene (BCB), acrylic, polybenzoxazole (PBO). Having a polymer core 302 may enable the first via 104 to provide structural support, [0037].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the via 56 to have a polymer core made of polyimide as taught by Lan in order to provide improved structural support to the electronic component 26. As a result, the polymer core would correspond to the claimed plug material at least partially surrounded by the varistor material of 56.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899