DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on January 23rd, 2026, has been entered.
Upon entrance of the Amendment, claims 2, 10-12, and 14 were amended. Claims 1-20 are currently pending.
Claim 10 was objected to because of informalities. Claim 10 has been amended as suggested. The objections of claim 10 has been overcome and is withdrawn.
Response to Arguments
Applicant's arguments filed on January 23rd, 2026 have been fully considered but they are not persuasive.
The Applicant has argued “Fig. 4C of Xiao does not disclose an integrated circuit (IC) device. Rather, Fig. 4C discloses a sheet or an electronic assembly at a stage of process.” The argument is not persuasive because:
Firstly, the recitation of integrated circuit (IC) device is solely recited in the preamble. When reading the preamble in the context of the entire claim, the recitation integrated circuit (IC) device is not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention’s limitations. Thus, the preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.
Secondly, in column 2, lines 37-44, Xiao states “systems and methods for manufacturing flexible electronics, such as large area flexible electronics based on thin film circuits, are described herein. In some embodiments, for example, the systems and methods described herein form electrical features (e.g., TFTs and other thin film circuits) directly on a glass substrate, and thin the glass substrate to serve as the base for the packaged flexible electronic components.” It is known in the art that electronic circuit package, electronic die/chip/component, microchip, semiconductor device, or TFT circuits, …. are all referred to an integrated circuit device.
The Applicant has argued “Fig. 4C of Xiao does not disclose an IC device with a plurality of regions on the sidewall, each region comprising a cavity in the sidewall. Rather, Xiao discloses recess 470 on top surface. One of ordinary skill would not understand the top surface of sheet 470 to be a sidewall of an IC device.” The argument is not persuasive because:
Firstly, there is no recitation of “an IC device with a plurality of regions on the sidewall, each region comprising a cavity in the sidewall” in the claim.
Second, elements 470 are cutting tracks, not a sheet.
Thirdly, Xiao does disclose “a plurality of regions on the sidewall, each region comprising a cavity in the sidewall” (Fig. 4C). Singulated substrates 221 with electronic features 230 on them form integrated circuit devices (Fig. 4D, electronic component 413, column 11, line 15).
Same responses are applied to the Applicant’s argument of “Makino does not disclose "an integrated circuit (IC) device comprising: ... a plurality of regions on the sidewall, each region comprising a cavity in the sidewall.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8, and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xiao et al. (U.S. Patent No. 11,264,279).
Regarding to claim 1, Xiao teaches an integrated circuit (IC) device comprising:
a substrate comprising a glass core (Fig. 4C, element 421, column 11, line 19), the glass core having a first surface (top surface), a second surface opposite the first surface (bottom surface), and a sidewall between the first surface and the second surface (Fig. 4C);
a build-up layer on at least the first surface (Fig. 4C, element 432/442, column 11, line 18); and
a plurality of regions on the sidewall, each region comprising a cavity in the sidewall, wherein the cavity (Fig. 4C, element 477):
spans a first distance in a first direction from the first surface toward the second surface (Fig. 4C, recess 470 on top surface spans from top surface toward bottom surface, the first distance is the height from top surface to the bottom of the trench); and
comprises a concave surface having a first depth at the first surface and a second depth at the first distance, the second depth being less than the first depth (Fig. 4, concave surface having a first depth at the top surface and a second depth at the bottom of the recess).
Regarding to claim 2, Xiao teaches the cavity comprises a cavity wall comprising a scalloped surf ace away from the first surface (column 3, lines 54-57, laser scribing process on glass forms scalloped surface profile).
Regarding to claim 3, Xiao teaches a first one of the plurality of regions is spaced apart from a second one of the plurality of regions (Fig. 4C).
Regarding to claim 4, Xiao teaches the sidewall further comprises an artifact of a mechanical sawing process in a space between the first region and the second region (Fig. 4D).
Regarding to claim 5, Xiao teaches a first one of the plurality of regions at least partially overlaps with a second one of the plurality of regions (Fig. 4C, recess 470 on the top surface overlaps with the recess 470 on the bottom surface).
Regarding to claim 6, Xiao teaches each region further comprises a second cavity in the
sidewall, wherein the second cavity:
spans a second distance from the second surface in a second direction toward the first surface (Fig. 4C, recess 470 on bottom surface spans from bottom surface toward top surface, the second distance is the height from bottom surface to the top valley of the recess); and
comprises a concave surface having a third depth at the second surface and a fourth depth at the second distance, the fourth depth being less than the third depth (Fig. 4, concave surface having a third depth at the bottom surface and a fourth depth at the valley of the recess).
Regarding to claim 8, Xiao teaches the first distance is less than half of a second distance between the first surface and the second surface (Fig. 4C).
Regarding to claim 10, Xiao teaches the build-up layer comprises a metallization layer and a dielectric material layer (Fig. 4C, electronic features 432 comprises a metallization layer and a dielectric material layer).
Claims 1, 3-4, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Makino et al. (U.S. Patent Application Publication No. 2014/0238952).
Regarding to claim 1, Makino teaches an integrated circuit (IC) device comprising:
a substrate comprising a glass core (Fig. 5(d), element 110c, Fig. 5(e), element 10, [0062], line 4), the glass core having a first surface (bottom surface), a second surface opposite the first surface (top surface), and a sidewall between the first surface and the second surface (Fig. 5(e));
a build-up layer on at least the first surface (Fig. 5(e), element 15); and
a plurality of regions on the sidewall, each region comprising a cavity in the sidewall, wherein the cavity (Fig. 4C, element Cb):
spans a first distance in a first direction from the first surface toward the second surface (Fig. 5(e), recess on bottom surface spans from bottom surface toward top surface of glass layer 10, the first distance is the height from bottom surface to the top point of the recess); and
comprises a concave surface having a first depth at the first surface and a second depth at the first distance, the second depth being less than the first depth (Fig. 5(e), concave surface having a first depth at the bottom surface and a second depth at the top point of the recess).
Regarding to claim 3, Makino teaches a first one of the plurality of regions is spaced apart from a second one of the plurality of regions (Fig. 5(e).
Regarding to claim 4, Makino teaches the first sidewall further comprises an artifact of a mechanical sawing process in a space between the first region and the second region (Fig. 5(g)).
Regarding to claim 9, Makino teaches the first distance is approximately equal to a distance between the first surface and the second surface (Fig. 5(f)).
Regarding to claim 10, Makino teaches the build-up layer comprises a metallization layer and a dielectric material layer (Fig. 5(f)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (U.S. Patent No. 11,264,279), as applied to claims 1 and 6 above, in view of Noda et al. (U.S. Patent No. 8,925,192).
Regarding to claim 7, Xiao does not disclose a distance between the first surface and the second surface is a sum of the first distance and the second distance. Noda discloses a distance between the first surface and the second surface is a sum of the first distance and the second distance (Fig. 3A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xiao in view of Noda to configure a distance between the first surface and the second surface to be a sum of the first distance and the second distance in order to simplify the final singulation step.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (U.S. Patent No. 11,264,279), as applied to claim 1 above, in view of Makino et al. (U.S. Patent Application Publication No. 2014/0238952).
Regarding to claim 9, Xiao does not disclose the first distance is approximately equal to a distance between the first surface and the second surface. Makino discloses first distance is approximately equal to a distance between the first surface and the second surface (Fig. 5f). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xiao in view of Makino to configure the first distance to be approximately equal to a distance between the first surface and the second surface in order to simplify the final singulation step.
Allowable Subject Matter
Claims 11-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 11, the prior art fails to anticipate or render obvious the claimed limitations including “at least one second region on the sidewall that includes a chipped portion or a portion containing a crack, wherein the at least one second region is outside of the first regions” in combination with the rest of limitations recited in claim 11.
Regarding to claim 14, the prior art fails to anticipate or render obvious the claimed limitations including “altering a microstructure of the glass substrate by treating a plurality of regions within singulation streets on the first surface with a laser” in combination with the rest of limitations recited in claim 14.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VU A VU/Primary Examiner, Art Unit 2897