DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species III in the reply filed on 01/02/2026 is acknowledged.
Claims 2, 7, 9-10, 12 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Claims 19-24 are cancelled pursuant to applicant’s amendment filed on 01/02/2026. Claims 2, 7, 12 and 17 were not expressly withdrawn by applicant’s response, however after further consideration these claims were determined to be required in non-elected Figure 1 and are therefore withdrawn from consideration. Election was made without traverse in the reply filed on 01/02/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 11 and 14-15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jeng et al. (US-20220359320-A1 – hereinafter Jeng).
Regarding claim 1, Jeng teaches an apparatus (Fig.3; ¶0058) comprising:
an interposer (Fig.3 110; ¶0058) comprising glass (¶0028);
one or more redistribution layers (Fig.3 112; ¶0030) on a first interposer surface (top surface of 110);
one or more conductive contacts (Fig.3 116; ¶0046) on a second interposer surface (bottom surface of 110) opposite the first interposer surface (top surface of 110);
one or more vias (Fig.3 111) through the interposer (110) coupling at least one of the conductive contacts (116) on the second interposer surface (bottom surface of 110) with the redistribution layers (112) on the first interposer surface (top surface of 110);
an integrated circuit device (Fig.3 120; ¶0041) embedded within a cavity in the interposer (110) between the first (top surface of 110) and second (bottom surface of 110) interposer surfaces, the embedded integrated circuit device (120) coupled with a first redistribution layers surface (bottom surface of 112);
a stack (devices 128 are not limited to a single chip, and a memory stack would fit this limitation; ¶0033) of two or more integrated circuit devices (Fig.3 128 left; ¶0033) coupled with a second redistribution layers surface (top surface of 112) opposite the first redistribution layers surface (bottom surface of 112); and
mold material (Fig.3 134; ¶0037) surrounding at least one side of the stack of two or more integrated circuit devices (128 left).
Regarding claim 4, Jeng teaches the apparatus of claim 1, wherein the embedded integrated circuit device (120) comprises a device chosen from the group consisting of: high bandwidth memory (HBM), intelligent power device (IPD), photonic integrated circuit (PIC), and embedded passive components (EPC) (¶0042).
Regarding claim 5, Jeng teaches the apparatus of claim 1, wherein a midpoint of the stack of two or more integrated circuit devices (128 left) is offset to a first side (left side) of a midpoint of the interposer (110), and wherein a midpoint of the embedded integrated circuit device (120) is offset to a second side (right side) of the midpoint of the interposer (110) opposite the first side (right side) of the midpoint of the interposer (110).
Regarding claim 11, Jeng teaches a system (Fig.3; ¶0058) comprising:
a host board (Fig.3 102; ¶0017);
an integrated circuit device package (Fig.3 depicts an IC package mounted on 102), the integrated circuit device package comprising:
an interposer (Fig.3 110; ¶0058) comprising glass (¶0028);
one or more redistribution layers (Fig.3 112; ¶0030) on a first interposer surface (top surface of 110);
one or more conductive contacts (Fig.3 116; ¶0046) on a second interposer surface (bottom surface of 110) opposite the first interposer surface (top surface of 110) and coupled to the host board (102);
one or more vias (Fig.3 111; ¶0029) through the interposer (110) coupling at least one of the conductive contacts (116) on the second interposer surface (bottom surface of 110) with the redistribution layers (112) on the first interposer surface (top surface of 110);
an integrated circuit device (Fig.3 120) embedded within a cavity in the interposer (110) between the first (top surface of 110) and second (bottom surface of 110) interposer surfaces, the embedded integrated circuit device (120) coupled with a first redistribution layers surface (bottom surface of 112);
a stack (devices 128 are not limited to a single chip, and a memory stack would fit this limitation; ¶0033) of two or more integrated circuit devices (Fig.3 128 left; ¶0033) coupled with a second redistribution layers surface (top surface of 112) opposite the first redistribution layers surface (bottom surface of 112); and
mold material (Fig.3 134; ¶0037) surrounding at least one side of the stack of two or more integrated circuit devices (128 left); and
a power supply (a power supply is an inherent feature of all semiconductor systems) to provide power to the integrated circuit device package (the package coupled to board 102) through the host board (102).
Regarding claim 14, Jeng teaches the system of claim 11, wherein the embedded integrated circuit device (120) comprises a device chosen from the group consisting of: high bandwidth memory (HBM), intelligent power device (IPD), photonic integrated circuit (PIC), and embedded passive components (EPC) (¶0042).
Regarding claim 15, Jeng teaches the system of claim 11, wherein a midpoint of the stack of two or more integrated circuit devices (128 left) is offset to a first side (left side) of a midpoint of the interposer (110), and wherein a midpoint of the embedded integrated circuit device (120) is offset to a second side (right side) of the midpoint of the interposer (110) opposite the first side (left side) of the midpoint of the interposer (110).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng in view of Shen et al. (US-20160013151-A1 – hereinafter Shen).
Regarding claim 3, Jeng teaches the apparatus of claim 1.
Jeng does not teach the apparatus further comprising one or more vias through the interposer coupling at least one of the conductive contacts on the second interposer surface with the embedded integrated circuit device.
Shen teaches an interposer (Fig.2 120.1; ¶0003 of Shen) with a cavity on the top side of the interposer (120.1 of Shen) and an integrated circuit device (Fig.2 110.2; ¶0003) disposed in the cavity, and a conductive via (Fig.2 204; ¶abstract) coupling the die (110.2 of Shen) through the interposer (120.1 of Shen).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the cavity in the interposer of Jeng (110 of Jeng) to be located on the opposite vertical side (top surface of 110 of Jeng) as shown by Shen (Fig.2 of Shen) with the corresponding IC device (120 of Jeng) and vias (111 of Jeng) accordingly flipped as well to arrive at the claimed invention. This difference is obvious to one of ordinary skill because it is a matter of design choice.
Regarding claim 13, Jeng teaches the system of claim 11.
Jeng does not teach the system further comprising one or more vias through the interposer coupling at least one of the conductive contacts on the second interposer surface with the embedded integrated circuit device.
Shen teaches an interposer (Fig.2 120.1; ¶0003 of Shen) with a cavity on the top side of the interposer (120.1 of Shen) and an integrated circuit device (Fig.2 110.2; ¶0003 of Shen) disposed in the cavity, and a conductive via (Fig.2 204; abstract of Shen) coupling the die (110.2 of Shen) through the interposer (120.1 of Shen).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the cavity in the interposer of Jeng (110 of Jeng) to be located on the opposite vertical side (top surface of 110 of Jeng) as shown by Shen (Fig.2 of Shen) with the corresponding IC device (120 of Jeng) and vias (111 of Jeng) accordingly flipped as well to arrive at the claimed invention. This difference is obvious to one of ordinary skill because it is a matter of design choice.
Claim(s) 6, 8, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng in view of Wang et al. (US-20240379496-A1 – hereinafter Wang).
Regarding claim 6, Jeng teaches the apparatus of claim 1.
Jeng does not teach the apparatus further comprising a frame coupled with the mold material surrounding at least one side of the stack of two or more integrated circuit devices, the frame adjacent at least the one side of the stack of two or more integrated circuit devices.
Wang teaches a stiffener ring (Fig.11A 1031; ¶0081 of Wang) made of copper (¶0081 of Wang) and surrounding one of more IC dies (Fig.4B 123 and 124; ¶0035 of Wang) while also located adjacent to the sides of the IC dies (123 and 124 of Wang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the copper stiffener ring of Wang (1031 of Wang) to surround the dies of Jeng (128 of Jeng) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of reducing package warpage.
Regarding claim 8, the aforementioned combination of Jeng in view of Wang from claim 6 teaches the apparatus of claim 6, wherein the frame (1031 of Wang) comprises copper (¶0081 of Wang).
Regarding claim 16, Jeng teaches the system of claim 11.
Jeng does not teach the system further comprising a frame coupled with the mold material surrounding at least one side of the stack of two or more integrated circuit devices, the frame adjacent at least the one side of the stack of two or more integrated circuit devices.
Wang teaches a stiffener ring (Fig.11A 1031; ¶0081 of Wang) made of copper (¶0081 of Wang) and surrounding one of more IC dies (Fig.4B 123 and 124; ¶0035 of Wang) while also located adjacent to the sides of the IC dies (123 and 124 of Wang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the copper stiffener ring of Wang (1031 of Wang) to surround the dies of Jeng (128 of Jeng) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of reducing package warpage.
Regarding claim 18, the aforementioned combination of Jeng in view of Wang from claim 16 teaches the apparatus of claim 16, wherein the frame (1031 of Wang) comprises copper (¶0081 of Wang).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US-20240079393-A1 and US-20230137691-A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817