DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 06/29/2026, with respect to the rejection(s) of claim(s) 1, 3-6, 8, 11, 13-16 and 18 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an alternative embodiment taught in primary reference Jeng.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-5, 11, and 13-15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jeng et al. (US-20220359320-A1 – hereinafter Jeng).
Regarding claim 1, Jeng teaches an apparatus (Fig.5; ¶0078) comprising:
an interposer (Fig.5 110; ¶0058) comprising glass (¶0028);
one or more redistribution layers (Fig.5 112; ¶0030) on a first interposer surface (top surface of 110);
one or more conductive contacts (Fig.5 116; ¶0046) on a second interposer surface (bottom surface of 110) opposite the first interposer surface (top surface of 110);
one or more vias (Fig.5 111; ¶0029) through the interposer (110) coupling at least one of the conductive contacts (116) on the second interposer surface (bottom surface of 110) with the redistribution layers (112) on the first interposer surface (top surface of 110);
an integrated circuit device (Fig.5 504; ¶0065) embedded within a cavity (Fig.5 depicts a cavity within interposer 110) within the first interposer surface (top surface of 110), the embedded integrated circuit device (504) coupled with a first surface of the redistribution layers (bottom surface of 112) that spans the cavity (Fig.5 depicts a cavity within interposer 110);
a stack (devices 506 are not limited to a single chip and could be drawn to a memory stack, which reads upon this limitation; ¶0067) of two or more integrated circuit devices (Fig.5 506 right; ¶0067) coupled with a second surface of the redistribution layers (top surface of 112), opposite the first surface of the redistribution layers (bottom surface of 112); and
mold material (Fig.5 512; ¶0071) surrounding at least one side of the stack of two or more integrated circuit devices (506 right).
Regarding claim 3, Jeng teaches the apparatus of claim 1, further comprising one or more vias (111) through the interposer (110) coupling at least one of the conductive contacts (116) on the second interposer surface (bottom surface of 110) with the embedded integrated circuit device (504).
Regarding claim 4, Jeng teaches the apparatus of claim 1, wherein the embedded integrated circuit device (504) comprises a device chosen from the group consisting of: high bandwidth memory (HBM), intelligent power device (IPD), photonic integrated circuit (PIC), and embedded passive components (EPC) (¶0066).
Regarding claim 5, Jeng teaches the apparatus of claim 1, wherein a midpoint of the stack of two or more integrated circuit devices (506 right) is offset to a first side (right side) of a midpoint of the interposer (110), and wherein a midpoint of the embedded integrated circuit device (504 left) is offset to a second side (left side) of the midpoint of the interposer (110) opposite the first side (right side) of the midpoint of the interposer (110).
Regarding claim 11, Jeng teaches a system (Fig.5 ¶0078) comprising:
a host board (Fig.5 102; ¶0017);
an integrated circuit device package (Fig.5 depicts an IC package device mounted on 102), the integrated circuit device package comprising:
an interposer (Fig.5 110; ¶0058) comprising glass (¶0028);
one or more redistribution layers (Fig.5 112; ¶0030) on a first interposer surface (top surface of 110);
one or more conductive contacts (Fig.5 116; ¶0046) on a second interposer surface (bottom surface of 110) opposite the first interposer surface (top surface of 110) and coupled to the host board (102);
one or more vias (Fig.5 111; ¶0029) through the interposer (110) coupling at least one of the conductive contacts (116) on the second interposer surface (bottom surface of 110) with the redistribution layers (112) on the first interposer surface (top surface of 110);
an integrated circuit device (Fig.5 504; ¶0065) embedded within a cavity (Fig.5 depicts a cavity within interposer 110) within the first interposer surface (top surface of 110), the embedded integrated circuit device (504) coupled with a first surface of the redistribution layers (bottom surface of 112) that spans the cavity (Fig.5 depicts a cavity within interposer 110);
a stack (devices 506 are not limited to a single chip and could be drawn to a memory stack, which reads upon this limitation; ¶0067) of two or more integrated circuit devices (Fig.5 506 right; ¶0067) coupled with a second surface of the redistribution layers (top surface of 112), opposite the first surface of the redistribution layers (bottom surface of 112); and
mold material (Fig.5 512; ¶0071) surrounding at least one side of the stack of two or more integrated circuit devices (506 right); and
a power supply (a power supply is an inherent feature of all semiconductor systems) to provide power to the integrated circuit device package (the package coupled to board 102) through the host board (102).
Regarding claim 13, Jeng teaches the system of claim 11, further comprising one or more vias (111) through the interposer (110) coupling at least one of the conductive contacts (116) on the second interposer surface (bottom surface of 110) with the embedded integrated circuit device (504).
Regarding claim 14, Jeng teaches the system of claim 11, wherein the embedded integrated circuit device (504) comprises a device chosen from the group consisting of: high bandwidth memory (HBM), intelligent power device (IPD), photonic integrated circuit (PIC), and embedded passive components (EPC) (¶0066).
Regarding claim 15, Jeng teaches the system of claim 11, wherein a midpoint of the stack of two or more integrated circuit devices (506 right) is offset to a first side (right side) of a midpoint of the interposer (110), and wherein a midpoint of the embedded integrated circuit device (504 left) is offset to a second side (left side) of the midpoint of the interposer (110) opposite the first side (right side) of the midpoint of the interposer (110).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 6, 8, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng in view of Wang et al. (US-20240379496-A1 – hereinafter Wang).
Regarding claim 6, Jeng teaches the apparatus of claim 1.
Jeng does not teach the apparatus further comprising a frame coupled with the mold material surrounding at least one side of the stack of two or more integrated circuit devices, the frame adjacent at least the one side of the stack of two or more integrated circuit devices.
Wang teaches a stiffener ring (Fig.11A 1031; ¶0081 of Wang) made of copper (¶0081 of Wang) and surrounding one of more IC dies (Fig.4B 123 and 124; ¶0035 of Wang) while also located adjacent to the sides of the IC dies (123 and 124 of Wang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the copper stiffener ring of Wang (1031 of Wang) to surround the dies of Jeng (506 of Jeng) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of reducing package warpage.
Regarding claim 8, the aforementioned combination of Jeng in view of Wang from claim 6 teaches the apparatus of claim 6, wherein the frame (1031 of Wang) comprises copper (¶0081 of Wang).
Regarding claim 16, Jeng teaches the system of claim 11.
Jeng does not teach the system further comprising a frame coupled with the mold material surrounding at least one side of the stack of two or more integrated circuit devices, the frame adjacent at least the one side of the stack of two or more integrated circuit devices.
Wang teaches a stiffener ring (Fig.11A 1031; ¶0081 of Wang) made of copper (¶0081 of Wang) and surrounding one of more IC dies (Fig.4B 123 and 124; ¶0035 of Wang) while also located adjacent to the sides of the IC dies (123 and 124 of Wang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the copper stiffener ring of Wang (1031 of Wang) to surround the dies of Jeng (504 of Jeng) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of reducing package warpage.
Regarding claim 18, the aforementioned combination of Jeng in view of Wang from claim 16 teaches the apparatus of claim 16, wherein the frame (1031 of Wang) comprises copper (¶0081 of Wang).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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